參數(shù)資料
型號(hào)： SII3124ACBHU
元件分類(lèi)： 總線控制器
英文描述： PCI BUS CONTROLLER, PBGA364
封裝： 21 X 21 MM, 1 MM PITCH, GREEN, BGA-364
文件頁(yè)數(shù)： 82/88頁(yè)
文件大小： 592K
代理商： SII3124ACBHU
PCI-X to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
2006 Silicon Image, Inc.
SiI-DS-0160-C
83
7.4 Internal Register Space – Base Address 2
These registers are 32-bits wide and provide Indirect Register Access to the registers of the SiI3124. Access to this register
space is through the PCI I/O space.
Address Offset
Register Name
00H
Global Register Offset
04H
Global Register Data
08H
Port Register Offset
0CH
Port Register Data
Table 7-10 SiI3124 Internal Register Space – Base Address 2
7.4.1
Global Register Offset
Address Offset: 00H
Access Type: Read/Write
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Reserved
Dword Offset
00
This register provides indirect addressing of a Global Register otherwise accessible directly via Base Address Register 0. The
Dword address offset for an indirect access is in bits 6 to 2; bits 31 to 7, 1, and 0 are reserved and should always be 0.
7.4.2
Global Register Data
Address Offset: 04H
Access Type: Read/Write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
As defined for indirectly accessed register
This register provides the indirect access addressed by the Global Register Offset register.
7.4.3
Port Register Offset
Address Offset: 08H
Access Type: Read/Write
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Reserved
Dword Offset
00
This register provides indirect addressing of a Port Register otherwise accessible directly via Base Address Register 1. The
Dword address offset for an indirect access is in bits 14 to 2; bits 31 to 15, 1, and 0 are reserved and should always be 0.
7.4.4
Port Register Data
Address Offset: 0CH
Access Type: Read/Write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
As defined for indirectly accessed register
This register provides the indirect access addressed by the Port Register Offset register.
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