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參數(shù)資料
| 型號(hào)： | SCD243110QCD |
| 廠商： | INTEL CORP |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 4 CHANNEL(S), 134.4K bps, SERIAL COMM CONTROLLER, PQFP100 |
| 封裝： | METRIC, QFP-100 |
| 文件頁(yè)數(shù)： | 98/186頁(yè) |
| 文件大?。?/td> | 2204K |
| 代理商： | SCD243110QCD |
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Advanced Multi-Protocol Communications Controller — CD2431
Datasheet
19
TXCOUT/DTR*
[0–3]
55, 59, 64,
68
O
TRANSMIT CLOCK OUT/DATA TERMINAL READY* [0–1]: This output can be
controlled automatically by the CD2431 to indicate a programmable threshold
has been reached in the receive FIFO. It can also be programmed to output the
transmit data clock. Following reset, this pin is high and stays high in Clock
mode until the transmit channel is enabled for the first time; after which it
remains active, independent of the state of the transmit enable. In all modes,
the clock transitions every bit time, even during idle fill in Asynchronous mode.
Data transitions are made on the negative-going edge of TXCOUT.
RXCOUT[0–3]
25, 32, 37,
47
O
RECEIVE CLOCK OUT [0–1]: This output provides a one-time bit rate clock for
the receive data in all modes, except when an input (RXCIN) one-time receive
clock is used. After reset, this pin is low until the channel is receive enabled for
the first time, after which it remains active, independent of the state of receive
enable. When in Asynchronous mode, the output only transitions while receiving
data and not during inter-character fill. The receive data is sampled on the
positive-going edge of this clock.
CTS*[0–3]
54, 58, 63,
67
I
CLEAR TO SEND* [0–1]: This input can be programmed to control the flow of
transmit data, for out-of-band flow control applications.
CD*[0–3]
85, 11, 18, 22
I
CARRIER DETECT* [0–1]: This pin is always visible in the MSVR register. The
CD input can be programmed to validate receive data.
TXCIN[0–3]
44, 48, 50,
52
I
TRANSMIT CLOCK [0–1]: This pin inputs the transmit clock to the bit rate
generator.
RXCIN[0–3]
43, 46, 49,
51
I
RECEIVE CLOCK [0–1]: This pin inputs the receive clock to the bit rate
generator.
DSR*[0–3]
53, 57, 61,
66
I
DATA SET READY* [0–1]: This pin is always visible in the MSVR register. The
DSR input can be programmed to validate receive data.
TXD[0–3]
39, 40, 41,
42
O
TRANSMIT DATA [0–1]: Serial data output for each channel.
RXD[0–3]
34, 35, 36,
38
I
RECEIVE DATA [0–1]: Serial data input for each channel.
BYTESWAP
31
I
BYTESWAP: This pin alters the byte ordering of data during certain 16-bit
transfers and changes the half of the data bus on which byte transfers are made
to comply with Intel or Motorola processor systems. BYTESWAP does not
alter the bus handshake signals. When the BYTESWAP pin is high, the byte of
A/D[0–7] precedes that of A/D[8–15] in a string of transmit or receive bytes;
when BYTESWAP is low, A/D[8–15] precedes A/D[0–7].
When the BYTESWAP pin is high, bytes are transferred on A/D[0–7] when A[0]
is low, and on A/D[8–15] when A[0] is high. When BYTESWAP is low, bytes are
transferred on A/D[8–15] when A[0] is low, and A/D[0–7] when A[0] is high. A
different register map is used, depending on the state of this pin.
Byteswap Byte Alignment
0
Motorola byte alignment
1
Intel byte alignment
VDD
8, 45, 79, 96
–
POWER
GND
2, 20, 62, 70,
82, 99
–
GROUND
Table 1.
Pin Descriptions (Sheet 3 of 3)
Symbol
Pin
Number
Type
Description
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參數(shù)描述 |
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