參數(shù)資料
型號: SC16C750BIBS
廠商: NXP Semiconductors N.V.
元件分類: 收發(fā)器
英文描述: 5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs
封裝: SC16C750BIA44<SOT187-2 (PLCC44)|<<http://www.nxp.com/packages/SOT187-2.html<1<week 41, 2004,;SC16C750BIA44<SOT187-2 (PLCC44)|<<http://www.nxp.com/packages/SOT187-2.html&l
文件頁數(shù): 18/44頁
文件大?。?/td> 212K
代理商: SC16C750BIBS
SC16C750B_5
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 17 October 2008
18 of 44
NXP Semiconductors
SC16C750B
5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs
7.3 FIFO Control Register (FCR)
This register is used to enable the FIFOs, clear the FIFOs, set the receive FIFO trigger
levels, and select the DMA mode.
7.3.1
DMA mode
7.3.1.1
Mode 0 (FCR bit 3 = 0)
Set and enable the interrupt for each single transmit or receive operation, and is similar to
the 16C450 mode. Transmit Ready (TXRDY) will go to a logic 0 whenever an empty
transmit space is available in the Transmit Holding Register (THR). Receive Ready
(RXRDY) will go to a logic 0 whenever the Receive Holding Register (RHR) is loaded with
a character.
7.3.1.2
Mode 1 (FCR bit 3 = 1)
Set and enable the interrupt in a block mode operation. The transmit interrupt is set when
the transmit FIFO is below the programmed trigger level. The receive interrupt is set when
the receive FIFO fills to the programmed trigger level. However, the FIFO continues to fill
regardless of the programmed level until the FIFO is full. RXRDY remains a logic 0 as long
as the FIFO fill level is above the programmed trigger level.
7.3.2
FIFO mode
Table 10.
Bit
7:6
FIFO Control Register bits description
Symbol
Description
FCR[7]
(MSB),
FCR[6] (LSB)
An interrupt is generated when the number of characters in the FIFO equals
the programmed trigger level. However, the FIFO will continue to be loaded
until it is full. Refer to
Table 11
.
FCR[5]
64-byte FIFO enable.
logic 0 = 16-byte mode (normal default condition)
logic 1 = 64-byte mode
FCR[4]
reserved
FCR[3]
DMA mode select.
logic 0 = set DMA mode ‘0’ (normal default condition).
logic 1 = set DMA mode ‘1’
Transmit operation in mode ‘0’:
When the SC16C750B is in the 16C450
mode (FIFOs disabled; FCR[0] = logic 0) or in the FIFO mode (FIFOs
enabled; FCR[0] = logic 1; FCR[3] = logic 0), and when there are no
characters in the transmit FIFO or transmit holding register, the TXRDY pin
will be a logic 0. Once active, the TXRDY pin will go to a logic 1 after the
first character is loaded into the transmit holding register.
Receive operation in mode ‘0’:
When the SC16C750B is in 16C450
mode, or in the FIFO mode (FCR[0] = logic 1; FCR[3] = logic 0) and there is
at least one character in the receive FIFO, the RXRDY pin will be a logic 0.
Once active, the RXRDY pin will go to a logic 1 when there are no more
characters in the receiver.
RCVR trigger. These bits are used to set the trigger level for the receive
FIFO interrupt.
5
4
3
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