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參數(shù)資料
| 型號(hào)： | SAA7390GP |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | High performance Compact Disc-Recordable CD-R controller |
| 中文描述： | 高性能式光盤CD - R光盤控制器 |
| 文件頁數(shù)： | 45/76頁 |
| 文件大?。?/td> | 366K |
| 代理商： | SAA7390GP |
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1996 Jul 02
45
Philips Semiconductors
Preliminary specification
High performance Compact
Disc-Recordable (CD-R) controller
SAA7390
Table 66
CSTS field descriptions
Notes
1.
2.
3.
4.
Normally NRQ is LOW during synchronization, header and EDC/ECC transmission.
RDY is set after command bit ACT is pulled LOW.
This is a fatal error which can be rectified only by restarting CDB2.
Interrupt sources are ACA = logic 1, LBT = logic 0 and HEF = logic 1.
Table 67
Block count registers: 0xF0D3 and 0xF0D4; note 1
Note
1.
This is a 16-bit down counter which should be programmed with the; number of blocks - 1. As soon as the count value
reaches zero, LBT is cleared and ATT is pulled LOW. LBT remains active for 13.3 ms at single speed record. Note
that the counter continue to decrement. New programmed information is used at the start of the next block.
Table 68
Header containing MSF address and mode: 0xF0D5, F0D6, F0D7 and F0DB
FIELD
LOGIC
DESCRIPTION
SAR
0
1
0
1
0
1
0
1
0
1
0
1
0
1
status not ready yet during this block; SAR cleared on each new block
status already read
no request to host will be issued
requests to host will be issued
data block transmission is in progress
data transmission is ceased
access to CDB2 is denied
access to CDB2 is allowed
state of block counter has reached zero
block counter is non zero
no error has occurred during communication with the host
an error has occurred in the host communication process; note 3
interrupt to microcontroller is asserted
no pending interrupts
NRQ
(1)
RDY
(2)
ACA
LBT
HEF
ATT
(4)
MNEMONIC
R/W
DATA BYTE
7
6
5
4
3
2
1
0
CBCL
CBCH
R/W
R/W
BLOCKCOUNT7 to BLOCKCOUNT0
BLOCKCOUNT15 to BLOCKCOUNT8
MNEMONIC
R/W
DATA BYTE
7
6
5
4
3
2
1
0
CMDE
CMIN
CSEC
CFRM
R/W
R/W
R/W
R/W
MODE1
MODE0
MINUTES7 to MINUTES0
SECONDS7 to SECONDS0
FRAME7 to FRAME0
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