
1996 Jul 02
20
Philips Semiconductors
Preliminary specification
High performance Compact
Disc-Recordable (CD-R) controller
SAA7390
8.3
Microprocessor interrupts
An interrupts pulse is generated upon completion of any of the following commands:
CALCULATE_SYNDROMES (not Mode 2, Form 1)
CALCULATE_SYNDROMES (Mode 2, Form 1)
CRC_RECALCULATE (not Mode 2, Form 1)
CRC_RECALCULATE (Mode 2, Form 1)
COPY_RESULTS (not Mode 2, Form 1)
COPY_RESULTS (Mode 2, Form 1)
CORRECT_P_SYNDROMES
CORRECT_Q_SYNDROMES
TEST_ECC_ROM
TEST_ECC_RAM_READ
TEST_ECC_RAM_WRITE.
If a command is aborted by the ASSERT_ABORT command, a spurious interrupt may be generated within five clock
cycles of the ASSERT_ABORT command.
Table 7
Command execution times; note 1
Note
1.
All times indicated reflect two clock cycles per memory access for all accesses other than P and Q corrections.
P and Q corrections reflect seven clock cycles per memory access. Execution times will be extended due to refresh
timing, other buffer traffic, and configuration of nibble-wide memory.
8.3.1
I
NTERRUPT REGISTER DEFINITIONS
Two registers are used to control the operation of the interrupt logic. The register INTRMSK allows each interrupt to be
enabled or disabled. INTRMSK and INTRFLG are cleared on reset to initially disable and clear all interrupts; the output
latch controlling the INT line is set on a reset; this must be cleared by writing 0x00 to INTRFLG. To enable an interrupt,
the bit that corresponds to the interrupt in INTRFLG must be set. The INTRFLG register shows the status of the
interrupts. If any bit is HIGH then an interrupt has occurred since the last time the bit was cleared. Writing a zero to any
COMMAND
CYCLES
TIME (
μ
s)
at 33 MHz
MEMORY
ACCESSES
CALCULATE_SYNDROMES (not Mode 2, Form 1)
CALCULATE_SYNDROMES (Mode 2, Form 1)
CRC_RECALCULATE (not Mode 2, Form 1)
CRC_RECALCULATE (Mode 2, Form 1)
COPY_RESULTS (not Mode 2, Form 1)
COPY_RESULTS (Mode 2, Form 1)
CORRECT_P_SYNDROMES
(maximum addition per correction)
CORRECT_Q_SYNDROMES
(maximum addition per correction)
TEST_ECC_RAM_READ
TEST_ECC_RAM_WRITE
5604
5600
4136
4120
1148
1156
1466
157
888
167
1184
1184
186.8
186.7
137.9
137.3
38.3
38.5
48.9
5.2
29.6
5.6
39.5
39.5
2658
2654
2068
2060
574
578
0
2
0
2
592
592