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參數(shù)資料
| 型號： | SAA7390 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | High performance Compact Disc-Recordable CD-R controller |
| 中文描述： | 高性能式光盤CD - R光盤控制器 |
| 文件頁數(shù)： | 37/76頁 |
| 文件大小： | 366K |
| 代理商： | SAA7390 |
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1996 Jul 02
37
Philips Semiconductors
Preliminary specification
High performance Compact
Disc-Recordable (CD-R) controller
SAA7390
Table 50
Last complete frame number: 0xF0E6, F0E7; note 1
Note
1.
This register provides the address of the last complete frame that was received.
11.3
ECC to buffer manager interface
The ECC logic is able to access the buffer manager frame memory in either byte or burst mode. The ECC logic provides
an offset address and uses a frame address programmed by the microcontroller, ECCFRM#. The logic can write a single
byte or variable number of bytes. In the event of an access to a variable number of bytes, the ECC logic will assert the
signal BURST and EREQ to indicate that a large number of cycles are requested.
For each read or write cycle, the buffer manager will toggle EACK HIGH for one clock cycle to indicate that one byte of
data has been read from or written to the memory. A single byte cycle will be the same with the exception that BURST
will remain negated (LOW). In the event of a higher priority memory access request during a burst cycle, EACK will
remain LOW for the duration of the higher priority access cycle. At the end of the higher priority access, the burst cycle
will resume and EACK will again toggle HIGH after each read or write is completed.
Table 51
ECC frame number address registers: 0xF0F4, F0F5; note 1
Note
1.
These registers provide the frame number address for ECC access to memory. The counter associated with these
registers is loaded after the most significant byte is written; the least significant byte must be written first to ensure
that the counter is loaded correctly. If a DRAM access is in progress that uses the address from the counter, the
update will be delayed until the access is completed.
MNEMONIC
R/W
DATA BYTE
7
6
5
4
3
2
1
0
LSTCMPFM
LSTCMPFM
R
R
FRAME7
FRAME6
FRAME5
FRAME4
FRAME3
FRAME2
FRAME1
FRAME0
FRAME10 to FRAME8
MNEMONIC
R/W
DATA BYTE
7
6
5
4
3
2
1
0
ECCFRM#
ECCFRM#
R/W
R/W
FRAME7
FRAME6
FRAME5
FRAME4
FRAME3
FRAME2
FRAME1
FRAME0
FRAME10 to FRAME8
ECCFRM# is used to determine the frame address for
all ECC operations. This register must be reloaded for
each frame accessed by the ECC.
11.4
SCSI to buffer manager interface
The host interface registers should be loaded prior to
starting an host interface transfer. The HOSTMOD register
should be loaded first. BYT/PAG and FAST from this
register are used to control the type of DRAM access used
by the host interface. If BYT/PAG is HIGH then burst mode
access cycles are selected; multiple CAS access cycles
are used to access data as fast as possible. FAST allows
the speed of the burst cycle to be selected; for most host
controllers this bit is set LOW to select three clocks per
CAS cycle. For faster host access, FAST should be
asserted and the host burst cycle uses two clocks perCAS
cycle.
RD_BUF from HOSTMOD controls the direction of data
flow to the buffer memory; this bit is kept LOW to allow
reading of data from the DRAM buffer. If RD_BUF is
asserted then host data will be written to the DRAM buffer.
OFF_ADR from HOSTMOD is used to select between one
and two offset mode for the host transfer. OFF_ADR LOW
selects single offset mode in which one block of data is
transferred for each frame of the buffer.
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相關代理商/技術參數(shù) |
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| SAA7392HL | 制造商:NXP Semiconductors 功能描述:CD-ROM INTERFACE, 80 Pin, Plastic, QFP |
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