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參數(shù)資料
| 型號： | SAA7390 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | High performance Compact Disc-Recordable CD-R controller |
| 中文描述： | 高性能式光盤CD - R光盤控制器 |
| 文件頁數(shù)： | 12/76頁 |
| 文件大?。?/td> | 366K |
| 代理商： | SAA7390 |
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1996 Jul 02
12
Philips Semiconductors
Preliminary specification
High performance Compact
Disc-Recordable (CD-R) controller
SAA7390
When the ten Q-channel registers have been updated,
QFRMRDY in RDDSTAT is set. The ten Q-channel
registers are valid while QFRMRDY is set. In the audio
mode, HDRRDY in RDDSTAT generates this interrupt, but
the QFRMRDY bit will still be available as status to the
microcontroller.
7.3.4
C-
FLAG RECEIVER
The C-flag bits, or corrector flags, are also 24 data clocks
long and reception of these bits is achieved using the
same method as for the sub-code; in this event, the C-flag
data is synchronized to the data.
The difference is that only one bit is used; F1, the absolute
time synchronization information. When in audio mode
and ENABRED in FECTL is set, receipt of F1 set will start
the internal data clock after the next rising edge of word
strobe (WSAB) which is the left channel sample when the
CD-60 decoder is programmed for EIAJ audio format.
When in audio mode, the Q-channel information provides
the MSF address and the F1 flag provides the start of
frame information; together these provide an absolute byte
address on the disc.
7.3.5
S2B UART
This UART is provided for communication with a second
slave microcontroller. It is hard-wired for one start-bit, eight
data bits, a parity bit and one stop bit. Parity testing can be
programmed to be either odd parity or even parity. Parity
error and over-run status are provided via PE and
OVRRUN in S2BSTAT. Selectable baud rates of
31.25, 62.5 and 187.5 kbaud are available via S2BSEL1
and S2BSEL0 in BRGSEL. Once the start-bit is found, the
data sampling time does not adapt dynamically, therefore
parity errors may occur depending on the baud rate
selected.
7.3.6
SPI UART
This UART is provided for communication with a second
slave microcontroller used in Philips CD-R engines.
7.3.7
W
ATCH
-
DOG TIMER
A pair of counters are included which output a 967
μ
s reset
pulse to the entire chip and the SYSRES and SYSRES
pins if the timer is not reset during the 212 ms time-out
period. The watch-dog timer is reset by setting RWMD in
FECTL HIGH then LOW. If RWMD is left HIGH, the
watch-dog function is disabled.
7.3.8
G
LUE
L
OGIC
(GLIC)
The final block of logic in the front-end consists of:
a programmable, linear pulse-width modulator for
spindle-motor control; an address de-multiplexer for the
address/data bus of the microcontroller; plus audio
multiplexing and muting circuitry for full control of Red
book audio data to an external Digital-to-Analog Converter
(DAC).
7.4
Track descriptor block
Logic has been included to simplify the creation of the
track descriptor block. This is achieved by allowing one
frame to be repeated a selectable number of times. Once
this repeated pattern is complete, the normal data is then
sent to the front-end.
相關(guān)PDF資料 |
PDF描述 |
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| SAA7390GP | High performance Compact Disc-Recordable CD-R controller |
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| SAA7707H | Shaft; Style: 1 - light; Applicable Model: LE-P / LEL-W |
| SAA7710T | High Quality Audio-Performance Digital Add-On Processor For Digital Sound Systems.(應(yīng)用在數(shù)字聲音系統(tǒng)的高品質(zhì)音頻性能數(shù)字附加處理器) |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SAA7390GP | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:High performance Compact Disc-Recordable CD-R controller |
| SAA7391 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:ATAPI CD-R block encoder/decoder |
| SAA7391H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:ATAPI CD-R block encoder/decoder |
| SAA7392 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Channel encoder/decoder CDR60 |
| SAA7392HL | 制造商:NXP Semiconductors 功能描述:CD-ROM INTERFACE, 80 Pin, Plastic, QFP |
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