參數(shù)資料
型號(hào): SAA7377GP
廠商: NXP SEMICONDUCTORS
元件分類: 消費(fèi)家電
英文描述: Force/Pressure transducer; Compensated; Pressure Range: 0 to 25 psi
中文描述: SPECIALTY CONSUMER CIRCUIT, PQFP64
文件頁數(shù): 49/56頁
文件大小: 311K
代理商: SAA7377GP
1998 Jul 06
49
Philips Semiconductors
Product specifications
Digital servo processor and Compact Disc
decoder (CD7)
SAA7377
12 OPERATING CHARACTERISTICS (MICROCONTROLLER INTERFACE TIMING)
V
DD
= 3.4 to 5.5 V; V
SS
= 0 V; T
amb
=
10 to +70
°
C; unless otherwise specified.
Notes
1.
Negative set-up time means that the data may change after clock transition.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Microcontroller interface timing (4-wire bus mode; writing to registers 0 to F; reading Q-channel subcode and
decoder status);
see Figs 33 and 34
I
NPUTS
SCL
AND
RAB
t
CL
t
CH
t
r
t
f
R
EAD MODE
(C
L
= 20 pF)
t
dRD
delay time RAB to SDA valid
t
PD
propagation delay SCL to SDA
t
dRZ
delay time RAB to SDA high-impedance
W
RITE MODE
((C
L
= 20 pF)
t
suD
set-up time SDA to SCL
t
hD
hold time SCL to SDA
t
suCR
set-up time SCL to RAB
t
dWZ
delay time SDA high-impedance to RAB
input LOW time
input HIGH time
rise time
fall time
500
500
480
480
ns
ns
ns
ns
700
50
980
50
ns
ns
ns
note 1
700
260
0
980
ns
ns
ns
ns
Microcontroller interface timing (4-wire bus mode; servo commands);
see Figs 35 and 36
I
NPUTS
SCL
AND
SILD
t
L
t
H
t
r
t
f
R
EAD MODE
(C
L
= 20 pF)
t
dLD
delay time SILD to SDA valid
t
PD
propagation delay SCL to SDA
t
dLZ
delay time SILD to SDA high-impedance
t
sCLR
set-up time SCL to SILD
t
hCLR
hold time SCL to SILD
W
RITE MODE
(C
L
= 20 pF)
t
sD
set-up time SDA to SCL
t
hD
hold time SCL to SDA
t
sCL
set-up time SCL to SILD
t
hCL
hold time SILD to SCL
t
dPLP
delay between two SILD pulses
t
dWZ
delay time SDA high-impedance to SILD
input LOW time
input HIGH time
rise time
fall time
710
710
240
240
ns
ns
ns
ns
480
830
25
950
50
ns
ns
ns
ns
ns
0
950
480
120
70
0
ns
ns
ns
ns
μ
s
ns
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