參數(shù)資料
型號(hào): SAA7374GP
廠商: NXP SEMICONDUCTORS
元件分類: 消費(fèi)家電
英文描述: Low voltage digital servo processor and Compact Disc decoder CD7LV
中文描述: SPECIALTY CONSUMER CIRCUIT, PQFP64
封裝: 14 X 14 MM, 2.70 MM HEIGHT, PLASTIC, MS-022, SOT-393-1, QFP-64
文件頁(yè)數(shù): 50/60頁(yè)
文件大小: 324K
代理商: SAA7374GP
1998 Feb 26
50
Philips Semiconductors
Product specification
Low voltage digital servo processor and
Compact Disc decoder (CD7LV)
SAA7374
11 OPERATING CHARACTERISTICS (I
2
S-BUS TIMING)
V
DD
= 3.0 to 3.6 V; V
SS
= 0 V; T
amb
=
10 to +70
°
C; unless otherwise specified.
Note
1.
The I
2
S-bus timing is directly related to the overspeed factor ‘n’ in the normal operating mode. In the lock-to-disc
mode ‘n’ is replaced by the disc speed factor ‘d’.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
I
2
S Timing (single speed
×
n);
(see Fig.32)
;
note 1
C
LOCK OUTPUT
: SCLK (CL = 20 pF)
T
cy
output clock period
sample rate = f
s
sample rate = 2f
s
sample rate = 4f
s
sample rate = f
s
sample rate = 2f
s
sample rate = 4f
s
sample rate = f
s
sample rate = 2f
s
sample rate = 4f
s
166/n
83/n
42/n
166/n
83/n
42/n
472.4/n
236.2/n
118.1/n
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
CH
clock HIGH time
t
CL
clock LOW time
O
UTPUTS
: WCLK, DATA
AND
EF (C
L
= 20 pF)
t
SU
set-up time
sample rate = f
s
sample rate = 2f
s
sample rate = 4f
s
sample rate = f
s
sample rate = 2f
s
sample rate = 4f
s
95/n
48/n
24/n
95/n
48/n
24/n
ns
ns
ns
ns
ns
ns
t
h
hold time
Fig.32 I
2
S-bus timing diagram.
VDD
0.8 V
VDD
0.8 V
tCH
MBG407
tCL
clock period Tcy
SCLK
WCLK
DATA
EF
th
tsu
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