參數(shù)資料
型號(hào)： SAA7373GP
廠商： NXP SEMICONDUCTORS
元件分類(lèi)： 消費(fèi)家電
英文描述： Digital servo processor and Compact Disc decoder CD7
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP64
文件頁(yè)數(shù)： 50/60頁(yè)
文件大小： 323K
代理商： SAA7373GP
1998 Jul 06
50
Philips Semiconductors
Product specification
Digital servo processor and Compact Disc
decoder (CD7)
SAA7373
11 OPERATING CHARACTERISTICS (I
2
S-BUS TIMING)
V
DD
= 3.4 to 5.5 V; V
SS
= 0 V; T
amb
=
10 to +70
°
C; unless otherwise specified
Note
1.
The I
2
S-bus timing is directly related to the overspeed factor ‘n’ in the normal operating mode. In the lock-to-disc
mode ‘n’ is replaced by the disc speed factor ‘d’.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
I
2
S-bus timing (single speed
×
n);
see Fig.32
;
note 1
C
LOCK OUTPUT
: SCLK (C
L
= 20 pF)
T
cy
output clock period
sample rate = f
s
sample rate = 2f
s
sample rate = 4f
s
sample rate = f
s
sample rate = 2f
s
sample rate = 4f
s
sample rate = f
s
sample rate = 2f
s
sample rate = 4f
s
166/n
83/n
42/n
166/n
83/n
42/n
472.4/n
236.2/n
118.1/n
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
CH
clock HIGH time
t
CL
clock LOW time
O
UTPUTS
: WCLK, DATA
AND
EF (C
L
= 20 pF)
t
su
set-up time
sample rate = f
s
sample rate = 2f
s
sample rate = 4f
s
sample rate = f
s
sample rate = 2f
s
sample rate = 4f
s
95/n
48/n
24/n
95/n
48/n
24/n
ns
ns
ns
ns
ns
ns
t
h
hold time
Fig.32 I
2
S-bus timing diagram.
VDD
0.8 V
VDD
0.8 V
tCH
MBG407
tCL
clock period Tcy
SCLK
WCLK
DATA
EF
th
tsu
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SAA7374 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:Low voltage digital servo processor and Compact Disc decoder CD7LV
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SAA7377GP 制造商:PHILIPS 制造商全稱(chēng):NXP Semiconductors 功能描述:Digital servo processor and Compact Disc decoder CD7
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