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參數資料
| 型號： | SAA7371GP |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | Digital servo processor and Compact Disc decoder CD7 |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | 14 X 14 MM, 2.70 MM HEIGHT, PLASTIC, MS-022, SOT-393-1, QFP-64 |
| 文件頁數： | 13/60頁 |
| 文件大小： | 247K |
| 代理商： | SAA7371GP |
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1998 Jul 06
13
Philips Semiconductors
Product specification
Digital servo processor and
Compact Disc decoder (CD7)
SAA7371
Fig.8 Subcode format and timing on pin V4.
n = disc speed.
W96
1
Q
R
S
T
U
V
W
1
Q
200/n
μ
s
min
11.3/n
μ
s
11.3/n
μ
s min
90/n
μ
s max
MBG401
7.6
FIFO and error corrector
The SAA7371 has a
±
8 frame FIFO. The error corrector is
a t = 2, e = 4 type, with error corrections on both C1
(32 symbol) and C2 (28 symbol) frames. Four symbols are
used from each frame as parity symbols. This error
corrector can correct up to two errors on the C1 level and
up to four errors on the C2 level.
The error corrector also contains a flag processor. Flags
are assigned to symbols when the error corrector cannot
ascertain if the symbols are definitely good. C1 generates
output flags which are read after (de-interleaving) by C2,
to help in the generation of C2 output flags.
The C2 output flags are used by the interpolator for
concealment of uncorrectable errors. They are also output
via the EBU signal (DOBM) and the EF output with I
2
S-bus
for CD ROM applications.
7.6.1
F
LAGS OUTPUT
(CFLG)
The flags output pin CFLG (open-drain) shows the status
of the error corrector and interpolator and is updated every
frame (7.35
×
n kHz). In the SAA7371 chip a 1-bit flag is
present on the CFLG pin as illustrated in Fig.9. This signal
shows the status of the error corrector and interpolator.
The first flag bit, F1, is the absolute time sync signal, the
FIFO-passed subcode sync and relates the position of the
subcode sync to the audio data (DAC output). This flag
may also be used in a super FIFO or in the synchronisation
of different players. The output flags can be made
available at bit 4 of the EBU data format (LSB of the 24-bit
data word), if selected by register A.
Fig.9 Flag output timing diagram.
handbook, full pagewidth
F1
F2
F3
F4
F5
F6
F7
F8
F1
F8
11.3/n
μ
s
33.9/n
μ
s
33.9/n
μ
s
MBG425
n = disc speed.
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| SAA7372 | Digital servo processor and Compact Disc decoder CD7 |
| SAA7373 | Digital servo processor and Compact Disc decoder CD7 |
| SAA7373GP | Digital servo processor and Compact Disc decoder CD7 |
| SAA7374 | Low voltage digital servo processor and Compact Disc decoder CD7LV |
| SAA7374GP | Low voltage digital servo processor and Compact Disc decoder CD7LV |
相關代理商/技術參數 |
參數描述 |
|---|---|
| SAA7372 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital servo processor and Compact Disc decoder CD7 |
| SAA7373 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital servo processor and Compact Disc decoder CD7 |
| SAA7373GP | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital servo processor and Compact Disc decoder CD7 |
| SAA7374 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Low voltage digital servo processor and Compact Disc decoder CD7LV |
| SAA7374GP | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Low voltage digital servo processor and Compact Disc decoder CD7LV |
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