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參數(shù)資料
| 型號(hào)： | SAA7324 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Digital servo processor and Compact Disc decoder with integrated DAC (CD10 II)(具有綜合數(shù)模轉(zhuǎn)換器（DAC）的數(shù)字伺服處理器和光盤譯碼器) |
| 中文描述： | 數(shù)字伺服處理器和光盤解碼器集成了援會(huì)（CD10型二）（具有綜合數(shù)模轉(zhuǎn)換器（DAC）的的數(shù)字伺服處理器和光盤譯碼器） |
| 文件頁(yè)數(shù)： | 20/68頁(yè) |
| 文件大小： | 285K |
| 代理商： | SAA7324 |
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2000 Jun 26
20
Philips Semiconductors
Product specification
Digital servo processor and Compact Disc
decoder with integrated DAC (CD10 II)
SAA7324
7.9
EBU interface
The bi-phase mark digital output signal at pin DOBM is in
accordance with the format defined by the IEC 958
specification. Three different modes can be selected via
decoder register A:
DOBM pin held LOW
Data taken before concealment, mute and fade (must
always be used for CD-ROM modes)
Data taken after concealment, mute and fade.
7.9.1
F
ORMAT
The digital audio output consists of 32-bit words
(‘subframes’) transmitted in bi-phase mark code (two
transitions for a logic 1 and one transition for a logic 0).
Words are transmitted in blocks of 384. The formats are
given in Table 6.
Table 6
Format
Table 7
Description of Table 6
Table 8
Bit assignment
FUNCTION
BITS
DESCRIPTION
Sync
Auxiliary
Error flags
Audio sample
Validity flag
User data
Channel status
Parity bit
0 to 3
4 to 7
4
8 to 27
28
29
30
31
not used; normally zero
CFLG error and interpolation flags when selected by register A
first 4 bits not used (always zero); 2’s complement; LSB = bit 12, MSB = bit 27
valid = logic 0
used for subcode data (Q-to-W)
control bits and category code
even parity for bits 4 to 30
FUNCTION
DESCRIPTION
Sync
The sync word is formed by violation of the bi-phase rule and therefore does not contain any data.
Its length is equivalent to 4 data bits. The 3 different sync patterns indicate the following situations:
sync B: start of a block (384 words), word contains left sample; sync M: word contains left sample
(no block start) and sync W: word contains right sample.
Left and right samples are transmitted alternately.
Audio samples are flagged (bit 28 = 1) if an error has been detected but was uncorrectable. This
flag remains the same even if data is taken after concealment.
Subcode bits Q-to-W from the subcode section are transmitted via the user data bit. This data is
asynchronous with the block rate.
The channel status bit is the same for left and right words. Therefore a block of 384 words contains
192 channel status bits. The category code is always CD. The bit assignment is given in Table 8.
Audio sample
Validity flag
User data
Channel status
FUNCTION
BITS
DESCRIPTION
Control
0 to 3
copy of CRC checked Q-channel control bits 0 to 3; bit 2 is logic 1 when
copy permitted; bit 3 is logic 1 when recording has pre-emphasis
always zero
CD: bit 8 = logic 1, all other bits = logic 0
set by register A; 10 = level I; 00 = level II; 01 = level III
always zero
Reserved mode
Category code
Clock accuracy
Remaining
4 to 7
8 to 15
28 to 29
6 to 27 and 30 to 191
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| SAA7324H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital servo processor and Compact Disc decoder with integrated DAC CD10 II |
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| SAA7325H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital servo processor and Compact Disc decoder with integrated DAC CD10 |
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