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參數(shù)資料
| 型號： | SAA7205 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | MPEG-2 systems demultiplexer |
| 中文描述： | MPEG - 2系統(tǒng)解復用器 |
| 文件頁數(shù)： | 38/84頁 |
| 文件大小： | 363K |
| 代理商： | SAA7205 |
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1997 Jan 21
38
Philips Semiconductors
Preliminary specification
MPEG-2 systems demultiplexer
SAA7205H
7.13
Output buffering for audio and video
Output buffering for both audio and video is based on
FIFOs and buffer control circuitry. For audio, a 6 kByte
buffer is needed in which data is written at byte clock
frequency (9 MHz). Data is output bit serially via pin
AUDAT, at AUDATCLK frequency, which is adjusted to the
bit rate of the audio data (32 to 448 kbit/s, or 9 Mbit/s
(software sync mode)). Alternatively, in audio/video
combined mode, audio data is output byte parallel at rates
determined by ‘a(chǎn)v_ratio’ (see Section “Interfacing to
SAA9042 and SAA5270 teletext decoders and SAA7183
EURO-DENC”). Valid audio elementary stream data is
indicated by AUDATV = 1. In case of buffer underflow,
AUDATV is kept LOW, unless the combined audio/video
mode is configured (see Fig.16). The audio FIFO is used
to overcome clock interfacing problems and to provide
sufficient delay to synchronize audio and video. The buffer
output process is controllable by the microcontroller
(see Section “Interfacing to SAA2500 and third party audio
decoders”).
The microcontroller can access the audio FIFO for
downloading ‘beeps’. For this purpose the microcontroller
has to program the audio interface to ‘
μ
c_downl’ = 1
(address 0x060A, see Table 13). Furthermore it has to
write valid audio PES packets (to addresses 0x1xxx),
including at least one valid PTS for the first frame, if the
audio interface is not programmed to PES mode or
software sync mode.
For video, a 768 Byte buffer is implemented which is filled
at byte clock frequency (9 MHz). The buffer is emptied on
the video decoder acquisition clock CLKP
(9 MHz = CCLKI/3, or lower rates in audio/video combined
mode). CLKP is gated to create a valid indicator. CLKP is
therefore frozen to logic 1 whenever the microcontroller
wants to communicate with the video decoder (VSEL = 0)
and in the event of buffer underflow.
A 2 kByte FIFO is incorporated for TXT data. The TXT
FIFO is filled at 9 MHz and is emptied at a rate of either
6.75 Mbit/s or 6.9375 Mbit/s (TXT insertion).
The microcontroller can access the FIFO to download TXT
pages. For this purpose the microcontroller has to program
the TXT interface to ‘txt_downl’ = 1 (address 0x0801,
see Table 13). Furthermore it has to write valid TXT pages
(to addresses 0x2000 to 0x23FF) in accordance with the
FIFO format specified in Fig.17.
7.14
Microcontroller interfacing
The microcontroller interface provides the means of
communication between a system controller (e.g. Philips
P90CE201) in a digital TV receiver and the demultiplexer
internal registers and buffers. The physical interface
consists of:
MDAT7 to MDAT0: an 8-bit wide bidirectional data bus.
Data and addresses information can be multiplexed on
this bus (optional).
CSDEM: an active LOW chip select signal.
The demultiplexer only responds to microcontroller
communication if this signal is driven LOW.
CSVID: an active LOW chip select signal for the video
decoder. The demultiplexer responds to a logic 1 on this
pin by putting MDAT7 to MDAT0 in high impedance
state should VSEL = 0. Consequently the
microcontroller is allowed to communicate with other
devices (i.e. RAMs and ROMs) when the demultiplexer
has a transparent control path set up between the
microcontroller and video decoder.
R/W: an active HIGH read signal indicating that the
microcontroller is attempting to read data from registers
or buffers inside the demultiplexer or the video decoder.
If this signal is LOW, data is being written to registers
inside the demultiplexer or video decoder.
MA10 to MA0: an 11-bit address bus. If bit MA10 = 1, it
indicates that direct addressing is applied and address
bits MA9 to MA2 are considered to be valid address
inputs. If MA10 = 0 normal indirect addressing is applied
and address bits MA9 to MA2 are ignored. The address
in this case is derived from the multiplexed data address
bus MDAT7 to MDAT0.
Direct addressing is applicable to a very restricted
number of demultiplexer registers only:
– MA9 to MA7: specify register unit numbers, so only
units in the range 0 to 7 are directly accessible
– MA6 to MA2: specify individual register addresses,
so only the first 32 registers (0 to 31) of a register unit
can be directly addressed. If address bit MA1 equals
logic 1, MDAT7 to MDAT0 carries address
information, otherwise it carries data (indirect
addressing mode). If the least significant address bit
(MA0) is logic 0, the most significant byte of a 16-bit
register is addressed, otherwise the least significant
byte is selected.
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相關代理商/技術參數(shù) |
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| SAA7205H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:MPEG-2 systems demultiplexer |
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| SAA7206H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:DVB compliant descrambler |
| SAA7207H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Reed Solomon decoder IC |
| SAA7207H/C1 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Reed Solomon decoder IC |
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