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參數(shù)資料
| 型號： | SAA7205 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | MPEG-2 systems demultiplexer |
| 中文描述： | MPEG - 2系統(tǒng)解復(fù)用器 |
| 文件頁數(shù)： | 29/84頁 |
| 文件大?。?/td> | 363K |
| 代理商： | SAA7205 |
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1997 Jan 21
29
Philips Semiconductors
Preliminary specification
MPEG-2 systems demultiplexer
SAA7205H
7.9
Interfacing to combined audio/video decoders
If the audio and video interfaces are programmed to the
A/V combined mode (av_combi = 1, address 0x060A,
see Table 13) they assume operation as illustrated in
Fig.16. The microcontroller controls the VO bus in much
the same way as described in Section “Interfacing to a
third party video decoder”. If VSEL = 0, the demultiplexer
sets up a transparent path between the microcontroller
and the combined A/V decoder (see Section “Interfacing to
a third party video decoder”). However, If the data level in
the video FIFO reaches a programmable overflow
threshold (‘v_ovfl’, address 0x0512, see Table 13), a
non-maskable interrupt (NMI) is pulled LOW. This
indicates that the microcontroller must release the VO bus,
otherwise video data is lost. As soon as the data level in
the video FIFO reaches the programmable underflow
threshold (‘v_undfl’, address 0x0512, see Table 13), NMI
is driven HIGH again.
Audio and video data are output at the request of the
combined A/V decoder, as illustrated in Fig.16 (VREQ,
AUDATR). If an A/V decoder does not have such a
request, these demultiplexer inputs may be grounded.
In the A/V combined mode, both CLKP and AUDATV can
be used as data valid signals (see Fig.16). Timing figures
for these valid signals are as indicated for CLKP in Fig.10.
Audio and video data are output in a sequence of, for
instance, four video bytes followed by one audio byte.
The length of this sequence is programmable and is
repeated incessantly. However, if the audio FIFO is empty,
or AUDATR is HIGH, a video byte is output, even in audio
time slots (see Fig.16), if VREQ is LOW. Audio data
however, are never output in video time slots.
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PDF描述 |
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| SAA7205H | MPEG-2 systems demultiplexer |
| SAA7206 | DVB compliant descrambler |
| SAA7206H | DVB compliant descrambler |
| SAA7216HS | Integrated MPEG AVGD decoders |
| SAA7221HS | Integrated MPEG AVGD decoders |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SAA7205H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:MPEG-2 systems demultiplexer |
| SAA7206 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:DVB compliant descrambler |
| SAA7206H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:DVB compliant descrambler |
| SAA7207H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Reed Solomon decoder IC |
| SAA7207H/C1 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Reed Solomon decoder IC |
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