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參數(shù)資料
| 型號： | SAA7205 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | MPEG-2 systems demultiplexer |
| 中文描述： | MPEG - 2系統(tǒng)解復(fù)用器 |
| 文件頁數(shù)： | 27/84頁 |
| 文件大小： | 363K |
| 代理商： | SAA7205 |
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1997 Jan 21
27
Philips Semiconductors
Preliminary specification
MPEG-2 systems demultiplexer
SAA7205H
The microcontroller must first force the audio interface to restart (
μ
c_frc_restart = 1). Subsequently it may download
compressed audio data by writing consecutive bytes to the audio buffer (address 0x1xxx, see Table 13). A ‘beep’ must
always consist of valid packetized elementary stream (PES) data. If the ‘beep’ is to be output to the audio decoder in
PES format, ‘a(chǎn)udio_pes’ must be set to logic 1. If the audio interface is programmed to software sync mode, the PES
headers do not have to contain PTS data words. However, if the ‘beep’ has to occur at a specific point in time, the
hardware sync mode (
μ
c_sw_sync = 0 and
μ
c_free_run = 1) is most suitable and at least the first PES header has to
contain a valid PTS.
Table 6
SAA2500 and third party audio output interface
PIN
I/O
MODE
FUNCTION
AUDAT
O
normal, SAA2500 and
gated clock
audio elementary stream data, clocked out 111 ns after an
AUDATCLK rising edge in 32 to 448 kHz mode, and 74 ns
after an AUDATCLK rising edge in 9 MHz mode
continuous audio data acquisition clock, 32 to 448 kHz, or
9 MHz
gated audio data acquisition mode, 32 to 448 kHz.
AUDATCLK = 0 in case of invalid data (gated_clock = 1,
address 0x060A, see Table 13)
continuous audio decoder chip clock (N
×
27 MHz/M)
ADATCLK
O
both normal and SAA2500
gated clock
AUDECLK
O
normal, SAA2500 and
gated clock
normal mode, gated clock
SAA2500 mode
normal mode, gated clock
SAA2500 mode
AUDATV
O
valid audio data indicator (microcontroller SAA2500 = 0)
audio sync word indicator (microcontroller SAA2500 = 1)
audio data error flag (active LOW)
sampling frequency indicator; logic 1 for 44.1 kHz, logic 0 for
the other frequencies
AUE
O
Fig.14 Audio descrambler clock circuit and programming examples.
handbook, full pagewidth
MGG776
+
12
27
f1
27
11.29
fo
12.288
1568
I0
1536
1914 (= 1568
+
4096
3750)
I1
2257 (= 1536
+
4096
3375)
2.392 (= 3750/1568)
M
2.197 (= 3375/1536)
0
I1
I0
1
12
Co
12
12 (b 0 to 11)
DFF
fo = 256fs
= 11.29 or 12.288 MHz
= AUDECLK
CCLKI
27 MHz
divide-by-M
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PDF描述 |
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| SAA7205H | MPEG-2 systems demultiplexer |
| SAA7206 | DVB compliant descrambler |
| SAA7206H | DVB compliant descrambler |
| SAA7216HS | Integrated MPEG AVGD decoders |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SAA7205H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:MPEG-2 systems demultiplexer |
| SAA7206 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:DVB compliant descrambler |
| SAA7206H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:DVB compliant descrambler |
| SAA7207H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Reed Solomon decoder IC |
| SAA7207H/C1 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Reed Solomon decoder IC |
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