- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄372114 > SAA7205 (NXP Semiconductors N.V.) MPEG-2 systems demultiplexer PDF資料下載
參數(shù)資料
| 型號(hào)： | SAA7205 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | MPEG-2 systems demultiplexer |
| 中文描述： | MPEG - 2系統(tǒng)解復(fù)用器 |
| 文件頁數(shù)： | 20/84頁 |
| 文件大?。?/td> | 363K |
| 代理商： | SAA7205 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁當(dāng)前第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁
1997 Jan 21
20
Philips Semiconductors
Preliminary specification
MPEG-2 systems demultiplexer
SAA7205H
Fig.9 Signal constellation for general purpose interface (SAA7201 compatible).
handbook, full pagewidth
MGG770
GPO7 to GPO0
byte 187
sync byte (0)
consecutive transport packet bytes
byte 1
tCLKOH
tCLKOL
bytes 2 to 187
GPST
GPSYNC
GPV
7.7
Interfacing to a third party video decoder
Communication to a third party video decoder involves
merging both video packetized elementary stream (PES)
or elementary stream (ES) data and control data on the
same 8-bit bidirectional bus VO7 to VO0 (see Fig.10).
PES or ES (bit: ‘video_pes_esn’, address 0x050A, see
Table 13) data is filtered by the video data filter and is
passed to a 768 Byte video FIFO buffer (see Section
“Output buffering for audio and video”), in which it is stored
at byte clock frequency (9 MHz). The video PES or ES
stream is read from the FIFO at video data acquisition
clock frequency CLKP (equals 9 MHz = CCLKI/3, 67%
duty cycle, see Fig.10). However, CLKP is a gated clock
signal, which is frozen to logic 1 in case of control
exchange between the microcontroller and the video
decoder (
VSEL = 0), or FIFO underflow (see Fig.10).
A bidirectional bus multiplexer (‘Merger’) is therefore
located at the output of the video FIFO. The timing
associated with the video output interface is illustrated in
Fig.11.
The third party video interface outputs clock and
synchronization references. The set of references consists
of a 13.5 MHz clock (CLK13.5, programmable phase, bit:
‘clk_13p5_pol’, address 0x050A, see Table 13), a CbREF
signal, “CCIR 601”compliant H, V, composite syncs, and
a field parity (EVEN/ODD) signal (both 50 Hz and 60 Hz,
bit: ‘ccir_50_60n’, address 0x050A, see Table 13).
The CbREF signal is locked to CCLKI and indicates
U samples in the UY/VY video decoder output.
To compensate for the delay in the decoding path, the
phase of CbREF (active LOW) is programmable as
illustrated in Fig.13 [bits: cb_ref_phase (1 to 0)], address
0x050A, see Table 13). The clock period immediately
following a COMSYNC falling edge in normal lines (equals
HSYNC falling edge) corresponds to counter position 0,
the clock period preceding the falling edge corresponds to
position 1727 (50 Hz), or 1715 (60 Hz),
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SAA7205H | MPEG-2 systems demultiplexer |
| SAA7206 | DVB compliant descrambler |
| SAA7206H | DVB compliant descrambler |
| SAA7216HS | Integrated MPEG AVGD decoders |
| SAA7221HS | Integrated MPEG AVGD decoders |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SAA7205H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:MPEG-2 systems demultiplexer |
| SAA7206 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:DVB compliant descrambler |
| SAA7206H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:DVB compliant descrambler |
| SAA7207H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Reed Solomon decoder IC |
| SAA7207H/C1 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Reed Solomon decoder IC |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。