參數(shù)資料
型號(hào): SAA7188
廠商: NXP Semiconductors N.V.
英文描述: Digital Video Encoder DENC2-M
中文描述: 數(shù)字視頻編碼器DENC2米
文件頁(yè)數(shù): 20/36頁(yè)
文件大?。?/td> 168K
代理商: SAA7188
1996 Jul 08
20
Philips Semiconductors
Preliminary specification
Digital Video Encoder (DENC2-M)
SAA7188A
Table 24
Logic levels and function of CCEN
Table 25
Logic levels and function of SRCM
Table 26
Subaddress 6E to 6F
Table 27
Subaddress 70
Note
1.
If cross-colour reduction is programmed, it is active between FAL and LAL in both events.
DATA BYTE
FUNCTION
CCEN1
CCEN0
0
0
1
1
0
1
0
1
line 21 encoding off
enables encoding in field 1 (odd)
enables encoding in field 2 (even)
enables encoding in both fields
DATA BYTE
AS OUTPUT
FUNCTION
SRCM1
SRCM0
0
0
1
0
1
0
VS
FS
Vertical Sync each field
Frame Sync (odd/even)
Field Sequence, vertical sync every fourth field (FISE = 1) or
eighth field (FISE = 0)
not applicable
FSEQ
1
1
DATA BYTE
DESCRIPTION
HTRIG
sets the Horizontal Trigger phase related to signal on RCV1 or RCV2 input
values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed
increasing HTRIG decreases delays of all internally generated timing signals
reference mark: analog output horizontal sync (leading slope) coincides with active edge of RCV
used for triggering at HTRIG = 032H
DATA BYTE
LOGIC LEVEL
DESCRIPTION
VTRIG
sets the vertical trigger phase related to signal on RCV1 input
increasing VTRIG decreases delays of all internally generated timing signals,
measured in half lines
variation range of VTRIG = 0 to 31 (1FH)
vertical blanking is defined by programming of FAL and LAL
vertical blanking is forced automatically at least during field synchronization and
equalization pulses; note 1
selects the phase reset mode of the colour subcarrier generator; see Table 28
SBLBN
0
1
PHRES
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