參數(shù)資料
型號(hào)： SAA7185
廠商： NXP Semiconductors N.V.
英文描述： Digital Video Encoder DENC2
中文描述： 數(shù)字視頻編碼器DENC2
文件頁(yè)數(shù)： 9/36頁(yè)
文件大?。?/td> 251K
代理商： SAA7185
1996 Jul 08
9
Philips Semiconductors
Preliminary specification
Digital Video Encoder (DENC2)
SAA7185
The DENC2 is
always
the timing master for the source at
the MP input. The IC provides two signals for
synchronizing this source:
On the RCM1 port the same signals as on RCV1 (as
output) are available; on RCM2 the IC provides a
horizontal pulse with programmable start and stop
phase.
The length of a field also start and end of its active part
can be programmed. The active part of a field always
starts at the beginning of a line.
Control interface
DENC2 contains two control interfaces: an I
2
C-bus slave
transceiver and 8-bit parallel microprocessor interface.
The interfaces cannot be used simultaneously.
The I
2
C-bus interface is a standard slave transceiver,
supporting 7-bit slave addresses and 100 kbits/s
guaranteed transfer rate. It uses 8-bit subaddressing with
an auto-increment function. All registers are write only,
except one readable status byte.
Two I
2
C-bus slave addresses can be selected
(pin SEL_MPU must be LOW):
88H: LOW at pin 61
8CH: HIGH at pin 61.
The parallel interface is defined by:
D7 to D0 data bus
CS active-LOW chip select signal
RW read/not write signal, LOW for a write cycle
DTACK 680xx style data acknowledge (handshake),
active-LOW
A0 register select, LOW selects address, HIGH selects
data.
The parallel interface uses two registers, one
auto-incremental containing the current address of a
control register (equals subaddress with I
2
C-bus control),
one containing actual data. The currently addressed
register is mapped to the corresponding control register.
The status byte can be read optionally via a read access
to the address register, no other read access is provided.
Input levels and formats
DENC2 expects digital YUV data with levels (digital codes)
in accordance with CCIR 601.
Deviating amplitudes of the colour difference signals can
be compensated by independent gain control setting,
while gain for luminance is set to predefined values,
distinguishable for 7.5 IRE set-up or without set-up.
The MPEG port accepts only 8-bit multiplexed CCIR 656
compatible data.
If the I
2
C-bus interface is used, the VP port can handle
both formats, 8-bit multiplexed Cb-Y-Cr data on the
VP lines, or the 16-bit DTV2 format with the Y signal on the
VP lines and the UV signal on the DP port.
Reference levels are measured with a colour bar,
100% white, 100% amplitude and 100% saturation.
相關(guān)PDF資料
PDF描述
SAA7186 Digital video scaler
SAA7188 Digital Video Encoder DENC2-M
SAA7188AWP AXIAL LEADED TUBULAR ALUMINUM RoHS Compliant: No
SAA7199 Digital Video Encoder DENC GENLOCK-capable
SAA7199BWP Digital Video Encoder DENC GENLOCK-capable
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SAA7185B 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital Video Encoders DENC2-M6
SAA7185BWP 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital Video Encoders DENC2-M6
SAA7185WP 制造商:NXP Semiconductors 功能描述: 制造商:Philips Semiconductor 功能描述:
SAA7186 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital video scaler
SAA7186H 制造商:NXP Semiconductors 功能描述:Factory Sealed Trays (120 Per box)
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