
1996 Oct 02
6
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
SAA7182A; SAA7183A
PINNING
SYMBOL
PIN
DESCRIPTION
PLCC84
QFP80
RESET
1
73
Reset input, active LOW. After reset is applied, all digital I/Os are in input mode.
The I
2
C-bus receiver waits for the START condition.
not connected
digital ground 1
The I
2
C-bus slave address select input pin. LOW: slave address = 88H,
HIGH = 8CH.
digital supply voltage 1 (3.3 V)
n.c.
V
SSD1
SA
2
3
4
6
75
V
DDD1
OVL2
OVL1
OVL0
KEY
DP0
DP1
DP2
DP3
V
DDD2
V
SSD2
DP4
DP5
DP6
DP7
TTXRQ
TTX
V
DDD3
n.c.
V
SSD3
MP7
MP6
MP5
MP4
V
DDD4
V
SSD4
MP3
MP2
MP1
MP0
RCV1
RCV2
5
6
7
8
9
13
77
78
79
80
1
2
3
4
5
14
7
8
9
10
11
12
28
20
15
16
17
18
19
29
21
22
23
24
25
26
3-bit overlay data input. This is the index for the internal look-up table.
Key input for OVL. When HIGH it selects OVL input.
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
Lower 4 bits of the data port. Input for multiplexed Cb, Cr data if 16 line input mode
is used.
digital supply voltage 2 (5 V)
digital ground 2
Upper 4 bits of the data port. Input for multiplexed Cb, Cr data if 16 line input mode
is used.
Teletext request output, indicating when bit stream is valid.
Teletext bit stream input.
digital supply voltage 3 (3.3 V)
not connected
digital ground 1
Upper 4 bits of MPEG port. It is an input for “CCIR 656” style multiplexed Cb, Y, Cr
data, or for Y data only, if 16 line input mode is used.
digital supply voltage 4 (5 V)
digital ground 4
Lower 4 bits of MPEG port. It is an input for “CCIR 656” style multiplexed Cb, Y, Cr
data, or for Y data only, if 16 line input mode is used.
Raster Control 1 for video port. This pin receives/provides a VS/FS/FSEQ signal.
Raster Control 2 for video port. This pin provides an HS pulse of programmable
length or receives an HS pulse.