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參數(shù)資料
| 型號： | SAA7182 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Digital Video Encoder EURO-DENC |
| 中文描述： | 數(shù)字視頻編碼器歐元，DENC |
| 文件頁數(shù)： | 19/40頁 |
| 文件大?。?/td> | 268K |
| 代理商： | SAA7182 |
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1996 Jul 08
19
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC)
SAA7182; SAA7183
Table 19
Subaddress 67 to 6A
Note
1.
LSBs of the respective bytes are encoded immediately after run-in and framing code, the MSBs of the respective
bytes have to carry the parity bit, in accordance with the definition of Line 21 encoding format.
Table 20
Subaddress 6B
DATA BYTE
(1)
DESCRIPTION
L21O0
L21O1
L21E0
L21E1
first byte of captioning data, odd field
second byte of captioning data, odd field
first byte of extended data, even field
second byte of extended data, even field
DATA BYTE
LOGIC LEVEL
DESCRIPTION
PRCV2
0
polarity of RCV2 as output is active HIGH, rising edge is taken when input; default
after reset
polarity of RCV2 as output is active LOW, falling edge is taken when input
pin RCV2 is switched to input; default after reset
pin RCV2 is switched to output
if ORCV2 = HIGH, pin RCV2 provides an HREF signal (Horizontal Reference Pulse
that is defined by RCV2S and RCV2E, also during vertical blanking Interval); default
after reset
1
0
1
0
ORCV2
CBLF
if ORCV2 = LOW, signal input to RCV2 is used for horizontal synchronization only
(if TRCV2 = 1); default after reset
if ORCV2 = HIGH, pin RCV2 provides a ‘Composite-Blanking-Not’ signal, for
example a reference pulse that is defined by RCV2S and RCV2E, excluding Vertical
Blanking Interval, which is defined by FAL and LAL (PRCV2 must be LOW)
1
if ORCV2 = LOW, signal input to RCV2 is used for horizontal synchronization
(if TRCV2 = 1) and as an internal blanking signal
polarity of RCV1 as output is active HIGH, rising edge is taken when input,
respectively; default after reset
polarity of RCV1 as output is active LOW, falling edge is taken when input,
respectively
pin RCV1 is switched to input; default after reset
pin RCV1 is switched to output
horizontal synchronization is taken from RCV1 port; default after reset
horizontal synchronization is taken from RCV2 port
defines signal type on pin RCV1; see Table 21
PRCV1
0
1
ORCV1
0
1
0
1
TRCV2
SRCV1
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SAA7182AWP | Digital Video Encoder EURO-DENC2 |
| SAA7183 | Digital Video Encoder EURO-DENC |
| SAA7182WP | Digital Video Encoder EURO-DENC |
| SAA7183WP | Digital Video Encoder EURO-DENC |
| SAA7185B | Digital Video Encoders DENC2-M6 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SAA7182A | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital Video Encoder EURO-DENC2 |
| SAA7182AWP | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital Video Encoder EURO-DENC2 |
| SAA7182WP | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital Video Encoder EURO-DENC |
| SAA7183 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital Video Encoder EURO-DENC |
| SAA7183A | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital Video Encoder EURO-DENC2 |
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