參數(shù)資料
型號: SAA7165
廠商: NXP SEMICONDUCTORS
元件分類: 消費家電
英文描述: Digital Video Encoder EURO-DENC2
中文描述: SPECIALTY CONSUMER CIRCUIT, PQCC44
封裝: PLASTIC, SOT-187, 44 PIN
文件頁數(shù): 37/45頁
文件大?。?/td> 203K
代理商: SAA7165
1996 Oct 02
37
Philips Semiconductors
Preliminary specification
Digital Video Encoder (EURO-DENC2)
SAA7182A; SAA7183A
Fig.17 Digital TV timing.
The data demultiplexing phase is coupled to the internal horizontal phase.
The CREF signal applies only for the 16 line digital TV format, because these signals are only valid in 13.5 MHz.
The phase of the RCV2 signal is programmed to tbf (tbf for 50 Hz) in this example in output mode (RCV2S).
handbook, full pagewidth
CREF
MP(n)
Y(0)
Cb(0)
Y(1)
Cr(0)
Y(2)
Cb(2)
Y(3)
Cr(2)
Y(4)
Cb(4)
DP(n)
RCV2
MBE739
Fig.18 RTCI timing.
(1) Sequence bit:
PAL = logic 0 then (R
Y) line normal; PAL = logic 1 then (R
Y) line inverted.
NTSC = logic 0 then no change.
(2) Reserved bits: 235 with 50 Hz systems; 232 with 60 Hz systems.
(3) Only from SAA7111 decoder.
(4) SAAA7111 provides (22 : 0) bits, resulting in 3 reserved bits before sequence bit.
handbook, full pagewidth
128
13
14
19
6768
01
0
0
21
RTCI
HPLL
increment
FSCPLL increment (4)
H/L transition
count start
4 bits
reserved
valid
sample
invalid
sample
not used in
SAA7182A/83A
sequence
bit (1)
reset
bit (3)
5 bits
reserved
8/LLC
reserved (2)
MGD673
LOW
time slot:
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