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參數(shù)資料
| 型號(hào)： | SAA7158WP |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | Back END IC |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁數(shù)： | 14/18頁 |
| 文件大?。?/td> | 117K |
| 代理商： | SAA7158WP |
July 1994
14
Philips Semiconductors
Preliminary specification
Back END IC
SAA7158
CHARACTERISTICS
Specification of input/output and clock levels and timing
The following table shows the specifications of input/output/clock levels and timing for
T
amb
= 0 to
+
70
°
C; V
DD
= 4.5 to 5.5 V; V
DDA
= 4.75 to 5.25 V unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supply
V
DD1-2
V
DDA1-4
I
DD1-2
I
DDA1-4
digital supply voltages
analog supply voltages
supply current digital
supply current analog
4.5
4.75
5.5
5.25
250
18
V
V
mA
mA
note 1
Digital inputs
V
IL
V
IH
I
LI
C
IC
C
ID
C
IZ
LOW level input voltage
HIGH level input voltage
input leakage current
input capacitance (clocks)
input capacitance (data)
input capacitance (I/O in high Z)
0.5
2.0
+
0.8
V
DD
+
0.5
10
10
10
10
V
V
μ
A
pF
pF
pF
Reference and current inputs
I
CUR
input current
0.4
mA
Digital outputs
V
OH
V
OL
HIGH level output voltage
LOW level output voltage
note 2
note 2
2.4
0
V
DD1-2
0.6
V
V
Timing
t
CLK
k
CLK
t
r
t
f
t
SU
t
HD
t
OH
t
OD
CLK cycle time
CLK duty cycle t
CLK-HIGH
/t
CLK
CLK rise time
CLK fall time
input data setup time
input data hold time
output data hold time
output data delay time
27
40
6
41
60
5
6
5
6
25
ns
%
ns
ns
ns
ns
ns
ns
note 2
note 2
Data output loads (3-state outputs)
C
ld
output load capacitance
10
35
pF
Characteristics of the DA converters
RSL
Y
RSL
C
B
CT
resolution of the Y DAC
resolution of the U and V DAC
analog signal bandwidth (
3 dB)
crosstalk between channels
20
9
8
42
bit
bit
MHz
dB
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