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參數(shù)資料
| 型號： | SAA7151 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Digital multistandard colour decoder with SCART interface DMSD2-SCART |
| 中文描述： | 數(shù)字彩色解碼器與多標準SCART接口DMSD2，SCART的 |
| 文件頁數(shù)： | 24/49頁 |
| 文件大?。?/td> | 311K |
| 代理商： | SAA7151 |
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April 1993
24
Philips Semiconductors
Product specification
Digital multistandard colour decoder with
SCART interface (DMSD2-SCART)
SAA7151B
Notes
1.
2.
Data output signals are Y7 to Y0 and UV7 to UV0. All other are control signals.
Levels are measured with load circuit. YUV-bus, HREF and VS outputs with 1.2 k
in parallel to 50 pF at 3 V
(TTL load);
LFCO output with 10 k
in parallel to 15 pF and other outputs with 1.2 k
in parallel to 25 pF at 3 V (TTL load).
Recommended crystal: Philips 4322 143 05291.
t
SU
, t
HD
, t
OH
and t
OD
include t
r
and t
f
.
3.
4.
Timing of YUV-bus and control outputs
Figures 10, 12 and 13
t
OH
output signal hold time
YUV, HREF, VS
at C
L
= 15 pF;
controls at C
L
= 7.5 pF
YUV, HREF, VS
at C
L
= 50 pF;
controls at C
L
= 25 pF
to 3-state condition
from 3-state condition
13
13
ns
ns
t
OS
output set-up time
20
20
22
20
ns
ns
ns
ns
t
SZ
t
ZS
data output disable transition time
data output enable transition time
Chrominance PLL
f
C
catching range
±
400
Hz
Crystal oscillator
Figures 19 and 20; note 3
f
n
f / f
n
nominal frequency
permissible deviation f
n
temperature deviation from f
n
crystal specification:
temperature range T
amb
load capacitance C
L
series resonance resistance R
S
motional capacitance C
1
parallel capacitance C
0
3rd harmonic
24.576
±
50
±
20
MHz
10
6
10
6
X1
0
8
40
1.5
±
20%
3.5
±
20%
70
80
°
C
pF
fF
pF
Line locked clock input LL27
(pin 27)
Fig.9 and 17
t
LL27
t
p
t
r
t
f
cycle time
duty factor
rise time
fall time
note 4
t
LL27H
/t
LL27
35
40
50
39
60
5
6
ns
%
ns
ns
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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