
1998 Apr 09
46
Philips Semiconductors
Product specification
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
SAA7146A
110
RPS_TO0
21
R
RPS time out error in Task 0
: this bit is set when the RPS
Task 0 stays longer than expected in the WAIT state. This bit
is reset by starting a new RPS Task 0.
RPS in UPLOAD
: this bit is active while RPS uploads the
working registers from the shadow RAM. The bit in the ISR is
set on the falling edge of this status bit.
DEBI Status
: this bit stays set as long as DEBI is processing
or halted by an error. The bit in the ISR is set on the falling
edge of this status bit, which indicates a ‘DEBI Done’.
DEBI Event
: this bit is set when one of the two DEBI event
flags (DEBI_EF or DEBI_TO) in the SSR is set. This bit is
reset when a new DEBI command starts. The reset value of
DEBI_TO is a logic 1.
I
2
C-bus Status
: this bit stays set as long as the I
2
C-bus is
transmitting data or halted by an error. The bit in the ISR is set
on the falling edge of this status bit, which indicates an ‘I
2
C
Done’.
I
2
C-bus Error
: this bit gets set when one of the I
2
C-bus status
bits in the SSR is set. This bit is reset when a new I
2
C-bus
transfer starts.
Audio input DMA2 protection
: this bit is set when the audio
input DMA2 address generation exceeded an ‘a(chǎn)ddress
boundary’ or hit its ‘limit’ (protection address). It is reset with
starting the DMA channel again.
Audio output DMA2 protection
: this bit is set when the audio
output DMA2 address generation exceeded an ‘a(chǎn)ddress
boundary’ or hit its ‘limit’ (protection address). It is reset with
starting the DMA channel again.
Audio input DMA1 protection
: this bit is set when the audio
input DMA1 address generation exceeded an ‘a(chǎn)ddress
boundary’ or hit its ‘limit’ (protection address). It is reset with
starting the DMA channel again.
Audio output DMA1 protection
: this bit is set when the audio
output DMA1 address generation exceeded an ‘a(chǎn)ddress
boundary’ or hit its ‘limit’ (protection address). It is reset with
starting the DMA channel again.
Audio FIFO Overflow/Underflow
: this bit gets set when one
of the four audio FIFOs has an underflow or overflow.
Video address Protection Error
: this bit is set when one of
the video DMAs 1 to 3 has an address protection error during
an active transmission.
Video FIFO Overflow/Underflow
: this bit is set if any of the
video FIFOs 1, 2 or 3 has an overflow or underflow.
UPLD
20
R
DEBI_S
19
R
DEBI_E
18
R
IIC_S
17
R
IIC_E
16
R
A2_in
15
R
A2_out
14
R
A1_in
13
R
A1_out
12
R
AFOU
11
R
V_PE
10
R
VFOU
9
R
OFFSET
(HEX)
NAME
BIT
TYPE
DESCRIPTION
RESET