參數(shù)資料
型號(hào)： SAA7140B
廠商： NXP SEMICONDUCTORS
元件分類(lèi)： 消費(fèi)家電
英文描述： High Performance Scaler HPS
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP128
文件頁(yè)數(shù)： 60/68頁(yè)
文件大小： 432K
代理商： SAA7140B
1996 Sep 04
60
Philips Semiconductors
Objective specification
High Performance Scaler (HPS)
SAA7140A; SAA7140B
Notes
1.
LLC
Scaler
may be LLC from DMSD port or LLCIN from expansion-port, dependent on scaler source clock selection
via I
2
C-bus bit LLCS.
Maximum T
VCLK
= 200 ns for test mode only. The applicable maximum cycle time depends on data format, horizontal
scaling and input data rate.
Measured at 1.5 V level; t
pL
may be infinite.
LLCIO
out
timing also valid for VCLKout in transparent mode; (see Fig.20).
Timings of VRO refer to the rising edge of VCLK.
The timing of INCADR and the rising edge of HFL always refers to LLC
Scaler
. During a VRAM transfer, the falling edge
of HFL is generated by VCLK. During horizontal increment and vertical reset cycles, both edges of HFL always refer
to LLC scaler.
Asynchronous signals. Its timing refers to the 1.5 V switching point of VOEN input signal (pin 53).
The timing refers to the 1.5 V switching point of VMUX signal (pin 46) in 32 to 16-bit multiplexing mode.
Corresponding pairs of VRO outputs are together connected.
2.
3.
4.
5.
6.
7.
8.
Data and control output timing at the expansion port, related to LLCIO output;
(see Fig.20)
C
L
t
OHD
load capacitance
output hold time
15
1.5
40
15
pF
ns
ns
ns
C
L
= 7.5 pF
C
L
= 15 pF
C
L
= 40 pF
t
PD
propagation delay from
positive edge of LLCIO output
VRO and reference signal output timing, related to VCLK output;
(see Fig.19)
C
L
output load capacitance
VRO outputs
other outputs
C
L
= 10 pF; note 5
C
L
= 10 pF; notes 6 and 1
15
7.5
0
0
40
25
pF
pF
ns
ns
t
OHD
t
OHL
VRO data hold time
related to LCC scaler
(INCADR, HFL)
related to VCLK (HFL)
VRO data delay time in
burst mode (TTR = 0)
VRO data delay time in
transparent mode (TTR = 1)
related to LCC
Scaler
(INCADR,HFL)
related to VCLK (HFL)
VRO disable time to 3-state
t
OHV
t
OD
C
L
= 10 pF; note 6
C
L
= 40 pF; note 5
0
25
ns
ns
C
L
= 40 pF; note 5
15
ns
t
ODL
C
L
= 25 pF; notes 6 and 7
60
ns
t
ODV
t
D
C
L
= 25 pF; note 6
C
L
= 40 pF; note 7
C
L
= 25 pF; note 8
C
L
= 40 pF; note 7
C
L
= 25 pF; note 8
no zooming
60
40
24
40
25
810
ns
ns
ns
ns
ns
ns
t
E
VRO enable time from 3-state
t
HFL VOE
HFL rising edge to VRAM port
enable
HFL rising edge to VCLK burst no zooming
t
HFL VCLK
840
ns
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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