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參數(shù)資料
| 型號： | SAA7140B |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | High Performance Scaler HPS |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP128 |
| 文件頁數(shù)： | 46/68頁 |
| 文件大?。?/td> | 432K |
| 代理商： | SAA7140B |
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1996 Sep 04
46
Philips Semiconductors
Objective specification
High Performance Scaler (HPS)
SAA7140A; SAA7140B
8.3
Description of the I
2
C-bus bits
Tables 15 to 21 give the function of the register bits given in Table 14.
8.3.1
I
NITIAL SETTINGS FOR THE EXPANSION AND
DMSD
PORT
;
SUBADDRESS
00H
Table 15
Field detection; data bits FICO1 to FICO0
Table 16
Reference edge selection for the V sync input of the field detection; data bit REVFLD
Table 17
Polarity selection for the H sync input of the field detection (note 1); data bit INVOE
Note
1.
INVOE may also be used for FDIO and FLDV output signal inversion
Table 18
Polarity of I
2
C-bus register set ID; data bit IREGS
Table 19
Fix I
2
C-bus register set ID; data bit SREGS
Table 20
Enable of reference signals PXQIO, HIO, VIO, FDIO, LLCIO (expansion port) and PXQV, HGTV, VSYV, FLDV
(VRAM port); data bit RSEN
FICO1
FICO0
DESCRIPTION
0
0
1
1
0
1
0
1
field sequence as detected from H and V sync signals
field sequence synchronized to H and V but noise limited
free running field sequence
reserved
REVFLD
DESCRIPTION
0
1
rising edge is reference
falling edge is reference
INVOE
DESCRIPTION
0
1
active LOW, e.g. for SAA71xx signals similar to HREF
active HIGH, e.g. for SAA71xx signals similar to HS
IREGS
DESCRIPTION
0
1
register set ID as defined by SREGS
register set ID inverted
SREGS
DESCRIPTION
0
1
register set ID toggles as detected and defined by FICO0 and FICO1
register set ID fixed to 1 (register set B selected)
RSEN
DESCRIPTION
0
1
reference signals enabled
reference signals disabled
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