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| 型號： | SAA7140B |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | High Performance Scaler HPS |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP128 |
| 文件頁數(shù)： | 16/68頁 |
| 文件大?。?/td> | 432K |
| 代理商： | SAA7140B |
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1996 Sep 04
16
Philips Semiconductors
Objective specification
High Performance Scaler (HPS)
SAA7140A; SAA7140B
7
FUNCTIONAL DESCRIPTION
The SAA7140A and SAA7140B accepts YUV data in a
16-bit wide parallel format at the DMSD port and accepts
YUV input in a 16-bit wide parallel format and in an 8-bit
byte-multiplexed Cb-Y-Cr-Y- format (CCIR-656 or
D1 oriented) at the expansion port.
Depending on the selected port modes, the incoming data
is formatted to the internal data representation, where
reference signals or codes are detected in the Data
Formatter/Reformatter (DFR). The horizontal and vertical
timing reference can be defined under I
2
C-bus control.
Based on that timing reference, the active processing
window is defined in a versatile way via the programming.
Two programming sets can be loaded simultaneously, and
become valid for processing in a field alternating way.
Before being processed in the central scaling unit, the
incoming data passes through the BCS control unit where
monitor control functions, for adjusting brightness, contrast
(luminance) and saturation (chrominance) are
implemented.
The scaling is performed in three steps:
1.
Horizontal prescaling (bandwidth limitation for
anti-aliasing, via FIR prefiltering and subsampling)
2.
Vertical scaling (generating phase interpolated or
vertically low-passed lines)
3.
Horizontal variable phase scaling (phase-correct
scaling to the new geometric relationships).
The scaled output data is fed back to the DFR unit and
may be used as output signals from the bidirectional
expansion port (if the mode is selected). They are
converted in parallel from the YUV to the RGB domain in a
digital matrix. Anti-gamma correction of gamma-corrected
input signals can be performed in the RGB data path.
The output formatter then formats the scaled data to one
of the various output formats (e.g. monochrome, 16-bit
YUV or 32-bit RGB (5, 5, 5).
To ease frame buffer applications, the data can be
transferred in a synchronous way (transparent mode),
using separate reference and qualifier signals and a
continuous output clock (VCLK). The data can also be
transferred in an asynchronous way (burst mode) using
the HFL and INCADR flags and a discontinuous input
clock burst on VCLK.
In a typical application, the 16-bit wide YUV input receives
clock, sync and data from a video decoder (SAA71xx) via
the DMSD port. An MPEG compression/decompression
circuit can be connected at the expansion port to receive
the decoder data, scaled or unscaled, or to deliver data to
the scaling processor. The scaling operation of the
SAA7140A and SAA7140B can be performed on the data
from a video decoder, or on the data from the
MPEG-codec at the expansion port input. The source
selection can be static or toggled on a field-by-field basis.
For example, during the odd field the video decoder signal
is scaled in accordance with the ‘odd’ parameter set for
display in a window. The compression codec receives
unscaled data. During the even field the decompressed
data from the MPEG decoder gets sized for a second
display window in accordance with the ‘even’ parameter
set. The resulting output from the scaling operation is
delivered via the 32-bit wide output (VRAM port) and to the
expansion port output (optional).
7.1
Data format/reformatter and reference signal
generation
The video data can be formatted/reformatted in
accordance with the selected expansion port mode, from
16-bit (DMSD port) to serial 8-bit (expansion port output),
from serial 8-bit (expansion port input) to internal parallel
16-bit format and from 24-bit (scaler output) to 16-bit/8-bit
respectively (expansion port output). The definition of the
timing references for the acquisition and field detection
(polarity and edge selection) are based on the selected
reference signal source. The field detector regenerates the
field information from the selected incoming reference
signals (see Fig.5).
The field sequence flag (FLD), detects the state of the
H-sync signal at the reference edge of the V-sync signal.
The detection is controlled by I
2
C-bus bits REVFLD and
INVOE. The detection output can be seen on pins FLDV
and FDIO (if FLDC = 0). Bits IREGS and SREGS control
the mapping of the detected sequence to the I
2
C-bus
register sets A and B (I
2
C-bus subaddress 02 to 1F and
22 to 3F).
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| SAA7144HL | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Quadruple video input processor |
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| SAA7146AH | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Multimedia bridge, high performance Scaler and PCI circuit SPCI |
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