
2003 Dec 09
30
Philips Semiconductors
Product specification
Digital video encoder
SAA7128AH; SAA7129AH
Table 52
Subaddress 6CH
Table 53
Subaddress 6DH
Table 54
Subaddress 6EH
Table 55
Selection of phase reset mode
BIT
SYMBOL
DESCRIPTION
7 to 0
HTRIG[7:0]
These are the 8 LSBs of the 11-bit code that sets the horizontal trigger phase related to
the signal on RCV1 or RCV2 input. The 3 MSBs are held in subaddress 6DH;
see Table 53. Values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed.
Increasing HTRIG[10:0] decreases delays of all internally generated timing signals.
Reference mark: analog output horizontal sync (leading slope) coincides with active
edge of RCV used for triggering at HTRIG[10:0] = 4FH (79).
BIT
SYMBOL
DESCRIPTION
7
6
5
4
3
2
1
0
HTRIG10
HTRIG9
HTRIG8
VTRIG4
VTRIG3
VTRIG2
VTRIG1
VTRIG0
These are the 3 MSBs of the horizontal trigger phase code; see Table 52.
Sets the vertical trigger phase related to signal on RCV1 input. Increasing VTRIG
decreases delays of all internally generated timing signals, measured in half lines;
variation range of VTRIG[4:0] = 0 to 31 (1FH).
BIT
SYMBOL
DESCRIPTION
7
SBLBN
0 = vertical blanking is defined by programming of FAL and LAL; default state after reset
1 = vertical blanking is forced in accordance with “ITU-R BT.624”(50 Hz) or RS170A
(60 Hz)
0 = encoder in normal operation mode
1 = output signal is forced to blanking level; default state after reset
These 2 bits select the phase reset mode of the colour subcarrier generator;
see Table 55.
6
BLCKON
5
4
3
2
1
0
PHRES1
PHRES0
LDEL1
LDEL0
FLC1
FLC0
These 2 bits select the delay on luminance path with reference to chrominance path;
see Table 56.
These 2 bits select field length control; see Table 57.
PHRES1
PHRES0
DESCRIPTION
0
0
1
1
0
1
0
1
no reset or reset via RTCI from SAA7111 if bit RTCE = 1; default value after reset
reset every two lines or SECAM specific if bit SECAM = 1
reset every eight fields
reset every four fields