- 您現(xiàn)在的位置：買賣IC網 > PDF目錄372113 > SAA7128AH (NXP SEMICONDUCTORS) Digital video encoder PDF資料下載
參數資料
| 型號： | SAA7128AH |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 顏色信號轉換 |
| 英文描述： | Digital video encoder |
| 中文描述： | COLOR SIGNAL ENCODER, PQFP44 |
| 封裝： | 10 X 10 MM, 1.75 MM HEIGHT, PLASTIC, SOT-307-2, QFP-44 |
| 文件頁數： | 20/55頁 |
| 文件大小： | 262K |
| 代理商： | SAA7128AH |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁當前第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁
2003 Dec 09
20
Philips Semiconductors
Product specification
Digital video encoder
SAA7128AH; SAA7129AH
Table 16
Subaddress 3AH
Table 17
Subaddresses 42H to 44H and 48H to 4AH
Table 18
Subaddresses 45H to 47H and 4BH to 4DH
Table 19
Subaddress 4EH
BIT
SYMBOL
DESCRIPTION
7
CBENB
0 = data from input ports is encoded; default state after reset
1 = colour bar with fixed colours is encoded
These 2 bits are reserved; each must be set to a logic 0.
6
5
4
SYMP
0 = horizontal and vertical trigger is taken from RCV2 and RCV1 respectively; default
state after reset
1 = horizontal and vertical trigger is decoded out of “ITU-R BT.656”compatible data at
MPEG port
0 = YC
B
C
R
-to-RGB dematrix is active; default state after reset
1 = YC
B
C
R
-to-RGB dematrix is bypassed
0 = CVBS output signal is switched to CVBS DAC; default state after reset
1 = advanced composite sync is switched to CVBS DAC
0 = input data is twos complement from MPEG port fader input
1 = input data is straight binary from MPEG port fader input; default state after reset
0 = input data is twos complement from Video port fader input
1 = input data is straight binary from Video port fader input; default state after reset
3
DEMOFF
2
CSYNC
1
MP2C
0
VP2C
ADDRESS
BYTE
DESCRIPTION
42H
48H
43H
49H
44H
4AH
KEY1LU
KEY1UU
KEY1LV
KEY1UV
KEY1LY
KEY1UY
Key colour 1 lower and upper limits for U, V and Y. If MPEG input signal is within the
limits of key colour 1 the incoming signals at the Video port and MPEG port are added
together according to the equation:
FADE1
×
video signal + (1
FADE1)
×
MPEG signal
Default value of all bytes after reset = 80H.
ADDRESS
BYTE
DESCRIPTION
45H
4BH
46H
4CH
47H
4DH
KEY2LU
KEY2UU
KEY2LV
KEY2UV
KEY2LY
KEY2UY
Key colour 2 lower and upper limits for U, V and Y. If MPEG input signal is within the
limits of key colour 2 the incoming signals at the Video port and MPEG port are added
together according to the equation:
FADE2
×
video signal + (1
FADE2)
×
LUT values
Default value of all bytes after reset = 80H.
BIT
SYMBOL
FADE1[5:0]
DESCRIPTION
7 to 6
5 to 0
These 2 bits are reserved; each must be set to logic 0.
These 6 bits form factor FADE1 which determines the ratio between the MPEG and
video input signal in the resulting video data stream if the key colour 1 is detected in the
MPEG input signal.
FADE1 = 00H: 100% MPEG, 0% video
FADE1 = 3FH: 100% video, 0% MPEG; this is the default value after reset
相關PDF資料 |
PDF描述 |
|---|---|
| SAA7129AH | Digital video encoder |
| SAA7129AH | Digital video encoder |
| SAA7128 | Digital video encoder |
| SAA7128H | Digital video encoder |
| SAA7129 | Digital video encoder |
相關代理商/技術參數 |
參數描述 |
|---|---|
| SAA7128H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital video encoder |
| SAA7129 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital video encoder |
| SAA7129/DENC29A | 制造商:NXP Semiconductors 功能描述: |
| SAA7129AH | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital video encoder |
| SAA7129AH/V1,518 | 功能描述:視頻 IC DIG VID ENCODER NTSC PAL SECAM RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復。