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參數(shù)資料
| 型號： | S9227 |
| 廠商： | Hamamatsu Photonics |
| 英文描述： | CMOS linear image sensor High-speed readout, simultaneous integration |
| 中文描述： | CMOS線性圖像傳感器高速讀出，同時(shí)整合 |
| 文件頁數(shù)： | 3/4頁 |
| 文件大小： | 108K |
| 代理商： | S9227 |
CMOS linear image sensor
S9227
I
Timing chart
KMPDC0166EB
3
Parameter
Symbol
tpw (ST)
thw (ST)
tlw (ST)
tr (ST), tf (ST)
tpw (CLK), T1
tr (CLK), tf (CLK)
tvd1
tvd2
Min.
Typ.
-
-
-
20
-
20
40
50
Max.
1100 ms
1000 ms
100 ms
30
20000
30
48
60
Unit
-
-
-
ns
ns
ns
ns
ns
Start pulse width
Start pulse high width
Start pulse low width
Start pulse rise and fall time
Clock pulse width
Clock pulse rise and fall time
Video delay time 1
Video delay time 2
Note: The internal circuit starts operating at the rise of CLK pulse immediately after ST pulse sets to low.
The integration time equals the high period of ST pulse plus 6 CLK cycles.
·
The output from 1st channel appears 14 clocks plus 100 ns after the falling edge of ST pulse.
·
The EOS pulse is output 25 ns after the falling edge of CLK pulse.
·
The output after reading the last pixel (512 ch) is indefinite.
T1
×
530 ns
T1
×
8 ns
T1
×
15 ns
0
200
0
32
40
tpw (CLK), T1
tlw (ST)
2.5 CLOCKS
8.5 CLOCKS
INTEGRATION TIME
1 2 3 4
13
CLK
ST
Video
EOS
CLK
ST
CLK
Video
1415
thw (ST)
tf (CLK)
tf (ST)
tr (ST)
tr (CLK)
tvd2
tvd1
tlw (ST)
thw (ST)
tpw (ST)
tpw (CLK)
tpw (ST)
512
Trig
I
Block diagram
CLK
8
KMPDC0167EA
TIMING
GENERATOR
SHIFT REGISTER
HOLD CIRCUIT
CHARGE AMP ARRAY
ST
7
1
2
3
4
PHOTODIODE
ARRAY
511 512
GND
1
6
5
Vdd
4
EOS
Video
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