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參數(shù)資料
| 型號(hào)： | S9132 |
| 廠商： | Hamamatsu Photonics |
| 英文描述： | Profile sensor High-speed frame rate sensor capable of acquiring two-dimensional projection data |
| 中文描述： | 簡(jiǎn)介傳感器高速幀速率傳感器獲取的二維投影數(shù)據(jù)的能力 |
| 文件頁(yè)數(shù)： | 2/6頁(yè) |
| 文件大?。?/td> | 153K |
| 代理商： | S9132 |
Profile sensor
S9132
2
I
Electrical characteristics (Ta=25 °C)
Parameter
Symbol
Min.
500
500
Typ.
-
-
-
Max.
5 M
10 M
-
-
-
0.15
30
60
30
60
-
Unit
10-bit MODE
8-bit MODE
Clock pulse frequency *
3
f (CLK)
Hz
Start pulse intervals
Video data rate
T (ST)
VR
VDO (H)
VDO (L)
3101/f (CLK)
-
Vdd (D)-0.15
-
-
-
-
-
-
s
f (CLK)/12
-
-
-
-
-
-
75
Hz
High level
Low level
CL=10 pF
CL=30 pF
CL=10 pF
CL=30 pF
Digital output voltage
V
Digital output rise time
(10 to 90 %)*
4
Digital output fall time
(10 to 90 %)*
4
Power consumption *
5
*3: Vdd (A)=Vdd (D)=5 V, V (CLK)=V (ST)=5 V, Vg=5 V (Low gain)
*4: CL: Load capacitance of digital output terminal
*5: Vdd (A)=Vdd (D)=5 V, V (CLK)=V (ST)=V (ST)=5 V, f (CLK)=5 MHz, f (ST)=1.5 kHz
tr
ns
tf
ns
P
mW
I
Electrical and optical characteristics [Ta=25 °C, Vdd (A)=Vdd (D)=5 V, V (CLK)=V (ST)=5 V]
Parameter
Symbol
Spectral response range
λ
Peak sensitivity wavelength
λ
p
High gain
Photo sensitivity *
6
Low gain
Dark current
I
D
Saturation charge
Qsat
High gain
Feedback capacitance
of charge amplifier *
7
Low gain
High gain
Dark output voltage *
8
Low gain
High gain
Saturation output
voltage
Low gain
Photo response non-uniformity *
9
PRNU
*6: Vg=5 V (Low gain), Vg=0 V (High gain)
*7:
λ
=780 nm
*8: Storage time Ts=100 ms
*9: Uniformity is defined under the condition that the device is uniformly illuminated by light which is 50 % of the saturation
exposure level and using 254 pixels excluding both ends pixels as follows:
PRNU=
V/V × 100 (%)
X: the average output of all pixels,
X: the difference from the maximum or minimum output and X
Min.
Typ.
Max.
Unit
nm
nm
380 to 1000
500
40
8
0.2
8
0.2
1
100
20
3.5
3
-
-
-
-
-
-
-
-
-
-
-
-
RES
V/nJ
0.6
-
-
-
300
60
-
-
±10
pA
pC
Cf
pF
Vd
mV
2.5
2.5
-
Vsat
V
-
%
I
Recommended terminal voltage
Parameter
Analog supply voltage
Digital supply voltage *
2
Gain selection terminal
voltage
AD mode selection
voltage
Symbol
Vdd (A)
Vdd (D)
Min.
4.75
3
0
Typ.
5
5
-
Vdd (A)
Vdd (A)
-
Vdd (D)
-
Vdd (D)
-
Max.
5.25
Vdd (A)
0.4
Vdd (A) +0.25
Vdd (A) +0.25
0.4
Vdd (D) +0.25
0.4
Vdd (D) +0.25
0.4
Unit
V
V
High gain
Low gain
10-bit MODE
8-bit MODE
High level
Low level
High level
Low level
Vg
Vdd (A) -0.25
Vdd (A) -0.25
0
Vdd (D) -0.25
0
Vdd (D) -0.25
0
V
Vsel
V
Clock pulse voltage
V (CLK)
V
Start pulse voltage
V (ST)
V
*2: When the latter-stage digital processing circuit is a 3.3 V family, the high level of digital output signal is 3.3 V when operated at
Vdd (A)=5 V, Vdd (D)=3.3 V.
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