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參數(shù)資料
| 型號： | S29PL-J70TFI010 |
| 廠商： | Spansion Inc. |
| 元件分類： | FLASH |
| 英文描述： | CMOS 3.0 Volt-only, Simultaneous-Read/Write Flash Memory with Enhanced VersatileIO Control |
| 中文描述： | CMOS 3V電壓供電，同步讀/寫Flash存儲器并有增強(qiáng)VersatileIO控制 |
| 文件頁數(shù)： | 60/96頁 |
| 文件大小： | 827K |
| 代理商： | S29PL-J70TFI010 |
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58
S29PL-J
S29PL-J_00_A9 September 22, 2006
D a t a
S h e e t
( A d v a n c e
I n f o r m a t i o n )
Figure 15.1
Program Operation
Note
See
Table 15.1 on page 62
for program command sequence.
15.6
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase algorithm. The device does
not
require the system to
preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical erase. The system is not required to provide any
controls or timings during these operations.
Table 15.1 on page 62
shows the address and data requirements
for the chip erase command sequence.
When the Embedded Erase algorithm is complete, that bank returns to the read mode and addresses are no
longer latched. The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/
BY#. Refer to
Write Operation Status
on page 64
for information on these status bits.
Any commands written during the chip erase operation are ignored.
Note that Secured Silicon Sector,
autoselect, and CFI functions are unavailable when a [program/erase] operation is in progress.
However,
note that a
hardware reset
immediately terminates the erase operation. If that occurs, the chip erase
command sequence should be reinitiated once that bank has returned to reading array data, to ensure data
integrity.
Figure 15.2 on page 59
illustrates the algorithm for the erase operation. Refer to the tables in
Erase/Program
Operations
on page 76
for parameters, and
Figure 20.8 on page 78
for timing diagrams.
START
Write Program
Command Sequence
Data Poll
from System
Verify Data
No
Yes
Last Address
No
Yes
Programming
Completed
Increment Address
Embedded
Program
algorithm
in progress
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| S29PL-J70TFI011 | CMOS 3.0 Volt-only, Simultaneous-Read/Write Flash Memory with Enhanced VersatileIO Control |
| S29PL-J70TFI012 | CMOS 3.0 Volt-only, Simultaneous-Read/Write Flash Memory with Enhanced VersatileIO Control |
| S29PL-J70TFI013 | CMOS 3.0 Volt-only, Simultaneous-Read/Write Flash Memory with Enhanced VersatileIO Control |
| S29PL-J70TFI020 | CMOS 3.0 Volt-only, Simultaneous-Read/Write Flash Memory with Enhanced VersatileIO Control |
| S29PL-J70TFI021 | CMOS 3.0 Volt-only, Simultaneous-Read/Write Flash Memory with Enhanced VersatileIO Control |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S29PL-J70TFI011 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:CMOS 3.0 Volt-only, Simultaneous-Read/Write Flash Memory with Enhanced VersatileIO Control |
| S29PL-J70TFI012 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:CMOS 3.0 Volt-only, Simultaneous-Read/Write Flash Memory with Enhanced VersatileIO Control |
| S29PL-J70TFI013 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:CMOS 3.0 Volt-only, Simultaneous-Read/Write Flash Memory with Enhanced VersatileIO Control |
| S29PL-J70TFI020 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:CMOS 3.0 Volt-only, Simultaneous-Read/Write Flash Memory with Enhanced VersatileIO Control |
| S29PL-J70TFI021 | 制造商:SPANSION 制造商全稱:SPANSION 功能描述:CMOS 3.0 Volt-only, Simultaneous-Read/Write Flash Memory with Enhanced VersatileIO Control |
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