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參數(shù)資料
| 型號： | S29GL128P10TFIV10 |
| 廠商： | SPANSION LLC |
| 元件分類： | PROM |
| 英文描述： | 3.0 Volt-only Page Mode Flash Memory featuring 90 nm MirrorBit Process Technology |
| 中文描述： | 128M X 1 FLASH 3V PROM, 100 ns, PDSO56 |
| 封裝： | 20 X 14 MM, LEAD FREE, MO-142EC, TSOP-56 |
| 文件頁數(shù)： | 68/80頁 |
| 文件大?。?/td> | 2706K |
| 代理商： | S29GL128P10TFIV10 |
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70
S29GL-P MirrorBit Flash Family
S29GL-P_00_A12 November 20, 2009
Da ta
Sh e e t
Table 12.2 S29GL-P Sector Protection Command Definitions, x16
Command (Notes)
Cyc
le
s
Bus Cycles (Notes 1–5)
First/Seventh
Second
Third
Fourth
Fifth
Sixth
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Loc
k
Regist
er
Command Set Entry
3
555
AA
2AA
55
555
40
Program (6)
2
XXX
A0
XXX
DATA
Read (6)
100
RD
2
XXX
90
XXX
00
Pa
s
w
o
rd
P
rot
ecti
on
Command Set Entry
3
555
AA
2AA
55
555
60
Password Program (9)
2
XXX
A0
PWA x
PWD x
Password Read (10)
4
00
PWD0
01
PWD 1
02
PWD 2
03
PWD 3
Password Unlock (10)
7
00
25
00
03
00
PWD 0
01
PWD 1
02
PWD 2
03
PWD 3
00
29
2
XXX
90
XXX
00
Gl
obal
No
n-V
o
latile
PPB Command Set Entry
3
555
AA
2AA
55
555
C0
XXX
A0
SA
00
All PPB Erase (13)
2
XXX
80
00
30
PPB Status Read (12)
1
SA
RD (0)
2
XXX
90
XXX
00
G
loba
l
V
o
latile
F
re
e
z
e
PPB Lock Command Set Entry
3
555
AA
2AA
55
555
50
PPB Lock Set (12)
2
XXX
A0
XXX
00
PPB Lock Status Read (12)
1
XXX
RD (0)
PPB Lock Command Set Exit (7, 8)
2
XXX
90
XXX
00
V
o
la
tile
DYB Command Set Entry
3
555
AA
2AA
55
555
E0
DYB Set (11, 12)2
XXX
A0
SA
00
DYB Clear (12)
2
XXX
A0
SA
01
DYB Status Read (12)
1
SA
RD (0)
DYB Command Set Exit (7, 8)
2
XXX
90
XXX
00
Legend
X = Don’t care
RD(0) = Read data.
SA = Sector Address. Address bits Amax–A16 uniquely select any sector.
PWD = Password
PWDx = Password word0, word1, word2, and word3.
Data = Lock Register Contents: PD(0) = Secured Silicon Sector Protection Bit,
PD(1) = Persistent Protection Mode Lock Bit, PD(2) = Password Protection
Mode Lock Bit.
Notes
1. See Table 7.1 on page 19 for description of bus operations.
2. All values are in hexadecimal.
3. All bus cycles are write cycles unless otherwise noted.
4. Data bits DQ15-DQ8 are don’t cares for unlock and command cycles.
5. Address bits AMAX:A16 are don’t cares for unlock and command cycles,
unless SA or PA required. (AMAX is the Highest Address pin.)
6. All Lock Register bits are one-time programmable. Program state = “0” and
the erase state = “1.” The Persistent Protection Mode Lock Bit and the
Password Protection Mode Lock Bit cannot be programmed at the same
time or the Lock Register Bits Program operation aborts and returns the
device to read mode. Lock Register bits that are reserved for future use
default to “1’s.” The Lock Register is shipped out as “FFFF’s” before Lock
Register Bit program execution.
7. The Exit command returns the device to reading the array.
8. If any Command Set Entry command was written, an Exit command must
be issued to reset the device into read mode.
9. For PWDx, only one portion of the password can be programmed per each
“A0” command.
10. Note that the password portion can be entered or read in any order as long
as the entire 64-bit password is entered or read.
11. If ACC = VHH, sector protection matches when ACC = VIH.
12. Protected State = “00h,” Unprotected State = “01h.”
13. The All PPB Erase command embeds programming of all PPB bits before
erasure.
相關(guān)PDF資料 |
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| S29GL032N90BFI32 | 2M X 16 FLASH 3V PROM, 90 ns, PBGA48 |
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| S2B | SURFACE MOUNT RECTIFIER |
| S2C1R-1-5-H | 4000 MHz - 8000 MHz RF/MICROWAVE SGL POLE DOUBLE THROW SWITCH, 1.7 dB INSERTION LOSS |
| S2D | SURFACE MOUNT RECTIFIER |
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