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參數(shù)資料
| 型號： | S29GL128P10TFIV10 |
| 廠商： | SPANSION LLC |
| 元件分類： | PROM |
| 英文描述： | 3.0 Volt-only Page Mode Flash Memory featuring 90 nm MirrorBit Process Technology |
| 中文描述： | 128M X 1 FLASH 3V PROM, 100 ns, PDSO56 |
| 封裝： | 20 X 14 MM, LEAD FREE, MO-142EC, TSOP-56 |
| 文件頁數(shù)： | 35/80頁 |
| 文件大?。?/td> | 2706K |
| 代理商： | S29GL128P10TFIV10 |
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40
S29GL-P MirrorBit Flash Family
S29GL-P_00_A12 November 20, 2009
Da ta
Sh e e t
Notes
1. DQ5 switches to 1 when an Embedded Program, Embedded Erase, or Write-to-Buffer operation has exceeded the maximum timing limits.
Refer toDQ5: Exceeded Timing Limits on page 39 for more information.
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
3. The Data# Polling algorithm should be used to monitor the last loaded write-buffer address location.
4. DQ1 switches to 1 when the device has aborted the write-to-buffer operation
7.9
Writing Commands/Command Sequences
During a write operation, the system must drive CE# and WE# to VIL and OE# to VIH when providing an
address, command, and data. Addresses are latched on the last falling edge of WE# or CE#, while data is
latched on the 1st rising edge of WE# or CE#. An erase operation can erase one sector, multiple sectors, or
the entire device. Table 6.1 – Table 6.4 indicate the address space that each sector occupies. The device
address space is divided into uniform 64KW/128KB sectors. A sector address is the set of address bits
required to uniquely select a sector. ICC2 in “DC Characteristics” represents the active current specification for
the write mode. “AC Characteristics” contains timing specification tables and timing diagrams for write
operations.
7.9.1
RY/BY#
The RY/BY# is a dedicated, open-drain output pin that indicates whether an Embedded Algorithm is in
progress or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse in the command
sequence. Since RY/BY# is an open-drain output, several RY/BY# pins can be tied together in parallel with a
pull-up resistor to VCC. This feature allows the host system to detect when data is ready to be read by simply
monitoring the RY/BY# pin, which is a dedicated output and controlled by CE# (not OE#).
7.9.2
Hardware Reset
The RESET# input provides a hardware method of resetting the device to reading array data. When RESET#
is driven low for at least a period of tRP (RESET# Pulse Width), the device immediately terminates any
operation in progress, tristates all outputs, resets the configuration register, and ignores all read/write
commands for the duration of the RESET# pulse. The device also resets the internal state machine to reading
array data.
To ensure data integrity Program/Erase operations that were interrupted should be reinitiated once the device
is ready to accept another command sequence.
When RESET# is held at VSS, the device draws VCC reset current (ICC5). If RESET# is held at VIL, but not at
VSS, the standby current is greater. RESET# may be tied to the system reset circuitry which enables the
system to read the boot-up firmware from the Flash memory upon a system reset. See Figure 11.7
on page 59 and Figure 11.8 on page 60 for timing diagrams.
Table 7.17 Write Operation Status
Status
DQ7
DQ6
DQ5
DQ3
DQ2
DQ1
RY/
BY#
Standard
Mode
Embedded Program Algorithm
DQ7#
Toggle
0
N/A
No toggle
0
Embedded Erase Algorithm
0
Toggle
0
1
Toggle
N/A
0
Program
Suspend
Mode
Program-
Suspend
Read
Program-Suspended
Sector
Invalid (not allowed)
1
Non-Program
Suspended Sector
Data
1
Erase
Suspend
Mode
Erase-
Suspend
Read
Erase-Suspended
Sector
1
No toggle
0
N/A
Toggle
N/A
1
Non-Erase
Suspended Sector
Data
1
Erase-Suspend-Program
(Embedded Program)
DQ7#
Toggle
0
N/A
0
Write-to-
Buffer
Busy (Note 3)
DQ7#
Toggle
0
N/A
0
Abort (Note 4)
DQ7#
Toggle
0
N/A
1
0
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