參數(shù)資料
型號： S29GL128P10TFIV10
廠商： SPANSION LLC
元件分類： PROM
英文描述： 3.0 Volt-only Page Mode Flash Memory featuring 90 nm MirrorBit Process Technology
中文描述： 128M X 1 FLASH 3V PROM, 100 ns, PDSO56
封裝： 20 X 14 MM, LEAD FREE, MO-142EC, TSOP-56
文件頁數(shù)： 30/80頁
文件大小： 2706K
代理商： S29GL128P10TFIV10
36
S29GL-P MirrorBit Flash Family
S29GL-P_00_A12 November 20, 2009
Da ta
Sh e e t
/* Example: Unlock Bypass Program Command
*/
/* Do while in Unlock Bypass Entry Mode!
*/
*( (UINT16 *)base_addr ) = 0x00A0;
/* write program setup command
*/
*( (UINT16 *)pa )
= data;
/* write data to be programmed
*/
/* Poll until done or error.
*/
/* If done and more to program, */
/* do above two cycles again.
*/
/* Example: Unlock Bypass Exit Command */
*( (UINT16 *)base_addr ) = 0x0090;
*( (UINT16 *)base_addr ) = 0x0000;
7.8
Write Operation Status
The device provides several bits to determine the status of a program or erase operation. The following
subsections describe the function of DQ1, DQ2, DQ3, DQ5, DQ6, and DQ7.
7.8.1
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Program or Erase algorithm
is in progress or completed, or whether the device is in Erase Suspend. Data# Polling is valid after the rising
edge of the final WE# pulse in the command sequence. Note that the Data# Polling is valid only for the last
word being programmed in the write-buffer-page during Write Buffer Programming. Reading Data# Polling
status on any word other than the last word to be programmed in the write-buffer-page returns false status
information.
During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum
programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend. When the
Embedded Program algorithm is complete, the device outputs the datum programmed to DQ7. The system
must provide the program address to read valid status information on DQ7. If a program address falls within a
protected sector, Data# polling on DQ7 is active, then that sector returns to the read mode.
During the Embedded Erase Algorithm, Data# polling produces a “0” on DQ7. When the Embedded Erase
algorithm is complete, or if the device enters the Erase Suspend mode, Data# Polling produces a “1” on DQ7.
The system must provide an address within any of the sectors selected for erasure to read valid status
information on DQ7.
After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling
on DQ7 is active for approximately 100 s, then the device returns to the read mode. If not all selected
sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the
selected sectors that are protected. However, if the system reads DQ7 at an address within a protected
sector, the status may not be valid.
Just prior to the completion of an Embedded Program or Erase operation, DQ7 may change asynchronously
with DQ6-DQ0 while Output Enable (OE#) is asserted low. That is, the device may change from providing
status information to valid data on DQ7. Depending on when the system samples the DQ7 output, it may read
Table 7.15 Unlock Bypass Program
(LLD Function = lld_UnlockBypassProgramCmd)
Cycle
Description
Operation
Byte Address
Word Address
Data
1
Program Setup
Write
Base + XXXh
00A0h
2
Program Command
Write
Program Address
Program Data
Table 7.16 Unlock Bypass Reset
(LLD Function = lld_UnlockBypassResetCmd)
Cycle
Description
Operation
Byte Address
Word Address
Data
1
Reset Cycle 1
Write
Base + XXXh
0090h
2
Reset Cycle 2
Write
Base + XXXh
0000h
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