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參數(shù)資料
| 型號： | S29GL128N11FAIV13 |
| 廠商： | SPANSION LLC |
| 元件分類： | DRAM |
| 英文描述： | 3.0 Volt-only Page Mode Flash Memory featuring 110 nm MirrorBit⑩ Process Technology |
| 中文描述： | 8M X 16 FLASH 3V PROM, 110 ns, PBGA64 |
| 封裝： | 13 X 11 MM, FBGA-64 |
| 文件頁數(shù)： | 47/100頁 |
| 文件大小： | 952K |
| 代理商： | S29GL128N11FAIV13 |
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S29GL-N_00_B3 October 13, 2006
S29GL-N MirrorBit Flash Family
45
D a t a S h e e t
Hardw are Data Protection
The command sequence requirement of unlock cycles for programming or erasing provides
data protection against inadvertent writes (refer to
Table 12 on page 63
and
Table 14 on
page 65
for command definitions). In addition, the following hardware data protection mea-
sures prevent accidental erasure or programming, which might otherwise be caused by
spurious system level signals during V
CC
power-up and power-down transitions, or from sys-
tem noise.
Low V
CC
W rite I nhibit
When V
CC
is less than V
LKO
, the device does not accept any write cycles. This protects data
during V
CC
power-up and power-down. The command register and all internal program/erase
circuits are disabled, and the device resets to the read mode. Subsequent writes are ignored
until V
CC
is greater than V
LKO
. The system must provide the proper signals to the control pins
to prevent unintentional writes when V
CC
is greater than V
LKO
.
W rite Pulse
Glitch
Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.
Logical I nhibit
Write cycles are inhibited by holding any one of OE# = V
IL
, CE# = V
IH
or WE# = V
IH
. To ini-
tiate a write cycle, CE# and WE# must be a logical zero while OE# is a logical one.
Pow er-Up W rite I nhibit
If WE# = CE# = V
IL
and OE# = V
IH
during power up, the device does not accept commands
on the rising edge of WE#. The internal state machine is automatically reset to the read mode
on power-up.
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