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參數(shù)資料
| 型號： | S29GL01GP12FACR13 |
| 廠商： | SPANSION LLC |
| 元件分類： | PROM |
| 英文描述： | 1G X 1 FLASH 3V PROM, 120 ns, PBGA64 |
| 封裝： | 13 X 11 MM, 1 MM PITCH, FBGA-64 |
| 文件頁數(shù)： | 64/80頁 |
| 文件大?。?/td> | 2706K |
| 代理商： | S29GL01GP12FACR13 |
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November 20, 2009 S29GL-P_00_A12
S29GL-P MirrorBit Flash Family
67
Data
She e t
11.7.5
Erase And Programming Performance
Notes
1. Typical program and erase times assume the following conditions: 25°C, 3.6 V VCC, 10,000 cycles, checkerboard pattern.
2. Under worst case conditions of -40°C, VCC = 3.0 V, 100,000 cycles.
3. Effective write buffer specification is based upon a 32-word write buffer operation.
4. In the pre-programming step of the Embedded Erase algorithm, all bits are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Tables 12.1–12.4.
11.7.6
TSOP Pin and BGA Package Capacitance
Notes
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C, f = 100 MHz.
Table 11.8 Erase And Programming Performance
Parameter
Typ
Max
Unit
Comments
Sector Erase Time
0.5
3.5
sec
Excludes 00h programming
prior to erasure (Note 4)
Chip Erase Time
S29GL128P
64
256
sec
S29GL256P
128
512
S29GL512P
256
1024
S29GL01GP
512
2048
Total Write Buffer Time (Note 3)
480
s
Excludes system level
overhead (Note 5)
Total Accelerated Write Buffer Programming Time
432
s
Chip Program Time
S29GL128P
123
sec
S29GL256P
246
S29GL512P
492
S29GL01GP
984
Table 11.9 Package Capacitance
Parameter Symbol
Parameter Description
Test Setup
Typ
Max
Unit
CIN
Input Capacitance
VIN = 0
6
10
pF
COUT
Output Capacitance
VOUT = 0
10
12
pF
CIN2
Control Pin Capacitance
VIN = 0
8
10
pF
WP#/ACC
Separated Control Pin
VIN = 0
42
45
pF
RESET#
Separated Control Pin
VIN = 0
25
28
pF
CE#
Separated Control Pin
VIN = 0
22
25
pF
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