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參數(shù)資料
| 型號： | S1C60L09D |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4-BIT, MROM, 0.08 MHz, MICROCONTROLLER, UUC70 |
| 封裝： | DIE-70 |
| 文件頁數(shù)： | 19/62頁 |
| 文件大?。?/td> | 476K |
| 代理商： | S1C60L09D |
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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports)
20
EPSON
S1C60N09 TECHNICAL MANUAL
4.5.4 I/O memory of I/O port
Table 4.5.4.1 lists the I/O port control bits and their addresses.
Table 4.5.4.1 I/O port control bits
Address
Comment
D3
D2
Register
D1
D0
Name
Init 1
10
07EH
TMRST SWRUN SWRST
IOC0
WR/W
TMRST3
SWRUN
SWRST3
IOC0
Reset
0
Reset
0
Reset
Run
Reset
Output
–
Stop
–
Input
Clock timer reset
Stopwatch timer Run/Stop
Stopwatch timer reset
I/O control register 0 (P00–P03)
07DH
P03
P02
P01
P00
R/W
P03
P02
P01
P00
– 2
High
Low
I/O port data (P00–P03)
Output latch is reset at initial reset
0FEH
000
IOC1
RR/W
0 3
IOC1
– 2
0
–
Output
–
Input
Unused
I/O control register 1 (P10–P13)
0FDH
P13
P12
P11
P10
R/W
P13
P12
P11
P10
– 2
High
Low
I/O port data (P10–P13)
Output latch is reset at initial reset
1
2
Initial value at initial reset
Not set in the circuit
3
4
Always "0" being read
Reset (0) immediately after being read
P00–P03, P10–P13: I/O port data registers (07DH, 0FDH)
I/O port data can be read and output data can be set through these registers.
Writing
When "1" is written: High level
When "0" is written: Low level
When an I/O port is set to the output mode, the written data is output from the I/O port terminal. When
"1" is written as the port data, the port terminal goes high (VDD), and when "0" is written, the terminal
goes low (VSS). Data can also be written in the input mode.
Reading
When "1" is read: High level
When "0" is read: Low level
The terminal voltage level of the I/O port is read out. When the I/O port is in the input mode the voltage
level being input to the port can be read; in the output mode the output voltage level can be read. When
the terminal voltage is high (VDD), the port data read is "1", and when the terminal voltage is low (VSS)
the data read is "0". Also, the built-in pull-down resistor functions during reading, so the I/O port
terminal is pulled down.
Note: When the I/O port is set to the input mode and a low-level voltage (Vss) is input, an erroneous
input results if the time constant of the capacitive load of the input line and the built-in pull-down
resistor load is greater than the read-out time. When the input data is being read, the time that the
input line is pulled down is equivalent to 0.5 cycles of the CPU system clock. Hence, the electric
potential of the terminals must settle within 0.5 cycles. If this condition cannot be met, some
measure must be devised, such as arranging a pull-down resistor externally, or performing multiple
read-outs.
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