參數(shù)資料
型號: RTL8201
廠商: Electronic Theatre Controls, Inc.
英文描述: REALTEK SINGLE CHIP SINGLE PORT 10/100M FAST ETHERNET PHYCEIVER RTL8201BL
中文描述: 瑞昱單片單端口10/100M自適應(yīng)快速以太網(wǎng)PHYCEIVER RTL8201BL
文件頁數(shù): 23/29頁
文件大?。?/td> 335K
代理商: RTL8201
RTL8201BL
2002-03-29
Rev.1.2
23
8.2.2 MII Timing of Reception Cycle
Shown is an example of transfer of a packet from PHY to MAC in MII interface
Symbol
Description
t
1
RXCLK high pulse width
Minimum
14
140
14
140
10
6
10
Typical
20
200
20
200
40
400
Maximum
26
260
26
260
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
100Mbps
10Mbps
100Mbps
10Mbps
100Mbps
10Mbps
100Mbps
10Mbps
100Mbps
t
2
RXCLK low pulse width
t
3
RXCLK period
t
4
RXER, RXDV, RXD[0:3] setup to
RXCLK rising edge
t
5
RXER, RXDV, RXD[0:3] hold after
RXCLK rising edge
10Mbps
100Mbps
10Mbps
100Mbps
10Mbps
100Mbps
6
ns
ns
ns
ns
ns
ns
130
600
240
600
150
t
6
Receive frame to CRS high
t
7
End of receive frame to CRS low
t
8
Receive frame to sampled edge of
RXDV
10Mbps
100Mbps
10Mbps
3200
120
800
ns
ns
ns
t
9
End of receive frame to sampled
edge of RXDV
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