參數(shù)資料
型號(hào)： PSD854F2A-90UT
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 256K X 8 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQFP64
封裝： ROHS COMPLIANT, TQFP-64
文件頁數(shù)： 81/128頁
文件大小： 1045K
代理商： PSD854F2A-90UT
PLDS
PSD8XXFX
Doc ID 7833 Rev 7
14.9
Input macrocells (IMC)
The CPLD has 24 input macrocells (IMC), one for each pin on ports A, B, and C. The
architecture of the input macrocells (IMC) is shown in Figure 16. The input macrocells (IMC)
are individually configurable, and can be used as a latch, register, or to pass incoming port
signals prior to driving them onto the PLD input bus. The outputs of the input macrocells
(IMC) can be read by the MCU through the internal data bus.
The enable for the latch and clock for the register are driven by a multiplexer whose inputs
are a product term from the CPLD AND Array or the MCU Address Strobe (ALE/AS). Each
product term output is used to latch or clock four input macrocells (IMC). port inputs 3-0 can
be controlled by one product term and 7-4 by another.
Configurations for the input macrocells (IMC) are specified by equations written in PSDabel
(see Application Note AN1171). outputs of the input macrocells (IMC) can be read by the
MCU via the IMC buffer (see Section 16: I/O ports).
Input macrocells (IMC) can use Address Strobe (ALE/AS, PD0) to latch address bits higher
than A15. Any latched addresses are routed to the PLDs as inputs.
Input macrocells (IMC) are particularly useful with handshaking communication applications
where two processors pass data back and forth through a common mailbox. Figure 17
shows a typical configuration where the Master MCU writes to the port A Data Out register.
This, in turn, can be read by the Slave MCU via the activation of the “Slave-Read” output
enable product term.
The Slave can also write to the port A input macrocells (IMC) and the Master can then read
the input macrocells (IMC) directly.
Note that the “Slave-Read” and “Slave-Wr” signals are product terms that are derived from
the Slave MCU inputs Read Strobe (RD, CNTL1), Write Strobe (WR, CNTL0), and
Slave_CS.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PSD854F2V-12JI 功能描述:CPLD - 復(fù)雜可編程邏輯器件 3.0V 2M 120ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
PSD854F2V-12MI 功能描述:CPLD - 復(fù)雜可編程邏輯器件 3.0V 2M 120ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
PSD854F2V-90J 功能描述:CPLD - 復(fù)雜可編程邏輯器件 3.0V 2M 90ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
PSD854F2V-90M 功能描述:CPLD - 復(fù)雜可編程邏輯器件 3.0V 2M 90ns RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
PSD-8M-01 制造商:Richco 功能描述:CB SPT REST MNT NAT 8MM SPC
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