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參數(shù)資料
| 型號： | PSD854F2A-90UT |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 256K X 8 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQFP64 |
| 封裝： | ROHS COMPLIANT, TQFP-64 |
| 文件頁數(shù)： | 67/128頁 |
| 文件大小： | 1045K |
| 代理商： | PSD854F2A-90UT |
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PSD8XXFX
Sector Select and SRAM Select
Doc ID 7833 Rev 7
12
Sector Select and SRAM Select
Sector Select (FS0-FS7, CSBOOT0-CSBOOT3) and SRAM Select (RS0) are all outputs of
the DPLD. They are setup by writing equations for them in PSDabel. The following rules
apply to the equations for these signals:
1.
Primary Flash memory and secondary Flash memory Sector Select signals must not
be larger than the physical sector size.
2.
Any primary Flash memory sector must not be mapped in the same memory space as
another Flash memory sector.
3.
A secondary Flash memory sector must not be mapped in the same memory space as
another secondary Flash memory sector.
4.
SRAM, I/O, and Peripheral I/O spaces must not overlap.
5.
A secondary Flash memory sector may overlap a primary Flash memory sector. In
case of overlap, priority is given to the secondary Flash memory sector.
6.
SRAM, I/O, and Peripheral I/O spaces may overlap any other memory sector. Priority is
given to the SRAM, I/O, or Peripheral I/O.
12.1
Example
FS0 is valid when the address is in the range of 8000h to BFFFh, CSBOOT0 is valid from
8000h to 9FFFh, and RS0 is valid from 8000h to 87FFh. Any address in the range of RS0
always accesses the SRAM. Any address in the range of CSBOOT0 greater than 87FFh
(and less than 9FFFh) automatically addresses secondary Flash memory segment 0. Any
address greater than 9FFFh accesses the primary Flash memory segment 0. You can see
that half of the primary Flash memory segment 0 and one-fourth of secondary Flash
memory segment 0 cannot be accessed in this example. Also note that an equation that
defined FS1 to anywhere in the range of 8000h to BFFFh would not be valid.
Figure 8 shows the priority levels for all memory components. Any component on a higher
level can overlap and has priority over any component on a lower level. Components on the
same level must not overlap. Level one has the highest priority and level 3 has the lowest.
12.2
Memory select configuration for MCUs with separate
program and data spaces
The 8031 and compatible family of MCUs, which includes the 80C51, 80C151, 80C251, and
80C51XA, have separate address spaces for program memory (selected using Program
Select Enable (PSEN, CNTL2)) and data memory (selected using Read Strobe (RD,
CNTL1)). Any of the memories within the PSD can reside in either space or both spaces.
This is controlled through manipulation of the VM register that resides in the CSIOP space.
The VM register is set using PSDsoft Express to have an initial value. It can subsequently
be changed by the MCU so that memory mapping can be changed on-the-fly.
For example, you may wish to have SRAM and primary Flash memory in the data space at
Boot-up, and secondary Flash memory in the program space at Boot-up, and later swap the
primary and secondary Flash memories. This is easily done with the VM register by using
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PSD854F2V-12JI | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 3.0V 2M 120ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| PSD854F2V-12MI | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 3.0V 2M 120ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| PSD854F2V-90J | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 3.0V 2M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| PSD854F2V-90M | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 3.0V 2M 90ns RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| PSD-8M-01 | 制造商:Richco 功能描述:CB SPT REST MNT NAT 8MM SPC |
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