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    參數(shù)資料
    型號: PSD4135G3V-C-15M
    廠商: 意法半導體
    英文描述: Flash In-System-Programmable Peripherals for 16-Bit MCUs
    中文描述: Flash在系統(tǒng)可編程外設的16位微控制器
    文件頁數(shù): 32/93頁
    文件大?。?/td> 503K
    代理商: PSD4135G3V-C-15M
    Preliminary Information
    PSD4000 Series
    29
    RESET
    DATA BUS
    R/W
    D0
    Q0
    Q1
    Q2
    Q3
    Q4
    Q5
    Q6
    Q7
    D1
    D2
    D3
    D4
    D5
    D6
    D7
    PAGE
    REGISTER
    PGR0
    PGR1
    PGR2
    PGR3
    DPLD
    AND
    GPLD
    INTERNAL
    SELECTS
    AND LOGIC
    FLASH
    PLD
    PGR4
    PGR5
    PGR6
    PGR7
    Figure 8. Page Register
    The
    PSD4000
    Functional
    Blocks
    (cont.)
    9.1.4 Page Register
    The eight bit Page Register increases the addressing capability of the microcontroller by a
    factor of up to 256. The contents of the register can also be read by the microcontroller.
    The outputs of the Page Register (PGR0-PGR7) are inputs to the PLD decoder and
    can be included in the Flash Memory, secondary Flash memory, and SRAM chip select
    equations.
    If memory paging is not needed, or if not all 8 page register bits are needed for memory
    paging, then these bits may be used in the PLD for general logic. See Application
    Notes.
    Figure 8 shows the Page Register. The eight flip flops in the register are connected to the
    internal data bus. The microcontroller can write to or read from the Page Register. The
    Page Register can be accessed at address location CSIOP + E0h.
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