• 參數(shù)資料
    型號: PSD411A2-C-70U
    廠商: 意法半導(dǎo)體
    英文描述: High Speed CMOS Logic Hex Schmitt-Triggered Inverters 14-SOIC -55 to 125
    中文描述: 低成本現(xiàn)場可編程微控制器外圍設(shè)備
    文件頁數(shù): 41/123頁
    文件大小: 657K
    代理商: PSD411A2-C-70U
    PSD4XX Famly
    38
    Pin
    Pin
    Pin
    Pin
    Pin
    Pin Name
    Function
    1
    RD
    Function
    2
    E
    Function
    3
    DS
    Function
    4
    LDS
    Function
    5
    RD
    WR
    WR
    R/W
    WRL
    PE0
    BHE
    PSEN
    WRH
    UDS
    SIZ0
    PE1
    ALE
    AD0
    A0
    BLE
    Table 6. Alternate Pin Functions
    9.2.2 PSD4XX Interface To a Multiplexed Bus
    Figure 20 shows a typical connection to a microcontroller with a multiplexed bus. The
    ADIO port of the PSD4XX is connected directly to the microcontroller address/data bus
    (AD0-AD15 for 16 bit bus). The ALE input signal latches the address lines internally. In a
    read bus cycle, data is driven out through the ADIO Port transceivers after the specified
    access time. The internal ADIO Port connection for a 16 bit multiplexed bus is shown in
    Figure 21. The ADIO Port is in tri-state mode if none of the PSD4XX internal devices are
    selected.
    9.2.3 PSD4XX Interface To Non-Multiplexed Bus
    Figure 22 shows a PSD4XX interfacing to a microcontroller with a non-multiplexed
    address/data bus. The address bus is connected to the ADIO Port, and the data bus is
    connected to Port C and/or Port D, depending on the bus width. There is no need for the
    ADIO Port to latch the address internally, but the user is offered the option to do so in the
    PSD4XX PSDsoft Software. The data Ports are in tri-state mode when the PSD4XX is not
    accessed by the microcontroller.
    The PSD4XX
    Architecture
    (cont.)
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