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參數(shù)資料
| 型號： | PCK2510SL |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 50-150 MHz 1:10 SDRAM clock driver |
| 中文描述： | 50-150兆赫1:10 SDRAM時(shí)鐘驅(qū)動器 |
| 文件頁數(shù)： | 2/10頁 |
| 文件大?。?/td> | 78K |
| 代理商： | PCK2510SL |
Philips Semiconductors
Product specification
PCK2510SL
50–150 MHz 1:10 SDRAM clock driver
2
2000 Dec 01
853–2231 25137
FEATURES
Phase-Locked Loop Clock distribution for
PC100/PC133 SDRAM applications
When outputs are disabled, the PLL and feedback output are
disabled, dropping AI
CC
to 100
μ
A in stand-by mode when input
clock signal is present.
See PCK2510SA for JEDEC compliant option where PLL remains
locked when outputs are disabled.
Spread Spectrum clock compatible
Operating frequency 50 to 150 MHz
(t
phase
error
– jitter) at 100 to133 MHz =
±
50 ps
Jitter (peak-peak) at 100 to 133 MHz =
±
80 ps
Jitter (cycle-cycle) at 100 to 133 MHz = 65 ps
Pin-to-pin skew
<
200 ps
Available in plastic 24-Pin TSSOP
Distributes one clock input to one bank of ten outputs
External Feedback (FBIN) terminal Is used to synchronize the
outputs to the clock input
On-Chip series damping resistors
No external RC network required
Operates at 3.3 V
See page 7 for Characteristic curves.
DESCRIPTION
The PCK2510SL is a high-performance, low-skew, low-jitter,
phase-locked loop (PLL) clock driver. It uses a PLL to precisely
align, in both frequency and phase, the feedback (FBOUT) output to
the clock (CLK) input signal. It is specifically designed for use with
synchronous DRAMs. The PCK2510SL operates at 3.3 V V
CC
and
is input compatible with both 2.5 V and 3.3 V input voltage ranges. It
also provides integrated series damping resistors that make it ideal
for driving point-to-point loads.
One bank of ten outputs provides ten low-skew, low-jitter copies of
CLK. Output signal duty cycles are adjusted to 50 percent,
independent of the duty cycle at CLK. All outputs can be enabled or
disabled via a single output enable input. When the G input is high,
the outputs switch in phase and frequency with CLK; when the G
input is low, the outputs are disabled to the logic-low state.
Unlike many products containing PLLs, the PCK2510SL does not
require external RC networks. The loop filter for the PLL is included
on-chip, minimizing component count, board space, and cost.
Because it is based on PLL circuitry, the PCK2510SL requires a
stabilization time to achieve phase lock of the feedback signal to the
reference signal. This stabilization time is required, following power
up and application of a fixed-frequency, fixed-phase signal at CLK,
and following any changes to the PLL reference. The PLL can be
bypassed for test purposes by strapping AV
CC
to ground.
The PCK2510SL is characterized for operation from 0
°
C to +70
°
C.
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
AGND
CLK
AV
CC
V
CC
V
CC
1Y9
1Y0
1Y8
GND
1Y1
GND
1Y6
1Y2
1Y7
1Y5
GND
V
CC
FBIN
GND
1Y3
1Y4
SW00382
V
CC
G
FBOUT
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
ORDER CODE
DRAWING NUMBER
24-Pin Plastic TSSOP
0
°
C to +70
°
C
PCK2510SLDH
SOT355-1
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PCK2510SA | 50-150 MHz 1:10 SDRAM clock driver |
| PCK2510S | 50-150 MHz 1:10 SDRAM clock driver |
| PCK2510SPW | 20 Characters x 4 Lines, 5x7 Dot Matrix Character and Cursor |
| PCK857 | 50-150MHz differential 1:10 SDRAM clock driver(50-150MHz 差分 1:10 SDRAM 時(shí)鐘驅(qū)動器) |
| PCK953 | 50-125 MHz PECL input/9 CMOS output 3.3 V PLL clock driver |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PCK2510SLDH | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:50-150 MHz 1:10 SDRAM clock driver |
| PCK2510SLDH,112 | 功能描述:鎖相環(huán) - PLL 50-150MHZ 1:10 SDRAM CLDR+STBY RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| PCK2510SPW | 制造商:NXP Semiconductors 功能描述:PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), 24 Pin Plastic SMT |
| PCK351 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1:10 clock distribution device with 3-State outputs |
| PCK351D | 功能描述:時(shí)鐘緩沖器 1:10 CLK DISTR DEV 3-ST OUTPUT RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
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