參數(shù)資料
型號(hào)： PCF85162T/1
廠商： NXP SEMICONDUCTORS
元件分類： 顯示驅(qū)動(dòng)器
英文描述： LIQUID CRYSTAL DISPLAY DRIVER, PDSO48
封裝： 6.10 MM, PLASTIC, MO-153, SOT362-1, TSSOP-48
文件頁(yè)數(shù)： 9/43頁(yè)
文件大小： 321K
代理商： PCF85162T/1
PCF85162_2
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 02 — 7 May 2010
17 of 43
NXP Semiconductors
PCF85162
Universal LCD driver for low multiplex rates
The following applies to Figure 11:
In static drive mode the eight transmitted data bits are placed in row 0 as one byte.
In 1:2 multiplex drive mode the eight transmitted data bits are placed in pairs into
row 0 and 1 as two successive 4-bit RAM words.
In 1:3 multiplex drive mode the eight bits are placed in triples into row 0, 1, and 2 as
three successive 3-bit RAM words, with bit 3 of the third address left unchanged. It is
not recommended to use this bit in a display because of the difficult addressing. This
last bit may, if necessary, be controlled by an additional transfer to this address but
care should be taken to avoid overwriting adjacent data because always full bytes are
transmitted.
In 1:4 multiplex drive mode, the eight transmitted data bits are placed in quadruples
into row 0, 1, 2, and 3 as two successive 4-bit RAM words.
7.11 Data pointer
The addressing mechanism for the display RAM is realized using the data pointer. This
allows the loading of an individual display data byte, or a series of display data bytes, into
any location of the display RAM. The sequence commences with the initialization of the
data pointer by the load-data-pointer command (see Table 11). Following this command,
an arriving data byte is stored at the display RAM address indicated by the data pointer.
The filling order is shown in Figure 11.
After each byte is stored, the content of the data pointer is automatically incremented by a
value dependent on the selected LCD drive mode:
In static drive mode by eight
In 1:2 multiplex drive mode by four
In 1:3 multiplex drive mode by three
In 1:4 multiplex drive mode by two
If an I2C-bus data access is terminated early then the state of the data pointer is unknown.
The data pointer should be re-written prior to further RAM accesses.
7.12 Subaddress counter
The storage of display data is determined by the contents of the subaddress counter.
Storage is allowed only when the content of the subaddress counter matches with the
hardware subaddress applied to A0, A1 and A2. The subaddress counter value is defined
by the device-select command (see Table 12). If the content of the subaddress counter
and the hardware subaddress do not match then data storage is inhibited but the data
pointer is incremented as if data storage had taken place. The subaddress counter is also
incremented when the data pointer overflows.
In cascaded applications each PCF85162 in the cascade must be addressed separately.
Initially, the first PCF85162 is selected by sending the device-select command matching
the first device's hardware subaddress. Then the data pointer is set to the preferred
display RAM address by sending the load-data-pointer command.
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