參數(shù)資料
型號(hào)： PCF85162T/1
廠商： NXP SEMICONDUCTORS
元件分類： 顯示驅(qū)動(dòng)器
英文描述： LIQUID CRYSTAL DISPLAY DRIVER, PDSO48
封裝： 6.10 MM, PLASTIC, MO-153, SOT362-1, TSSOP-48
文件頁(yè)數(shù)： 7/43頁(yè)
文件大?。?/td> 321K
代理商： PCF85162T/1
PCF85162_2
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 02 — 7 May 2010
15 of 43
NXP Semiconductors
PCF85162
Universal LCD driver for low multiplex rates
In the static drive mode the same signal is carried by all four backplane outputs and
they can be connected in parallel for very high drive requirements.
7.10 Display RAM
The display RAM is a static 32
× 4-bit RAM which stores LCD data. There is a one-to-one
correspondence between
the bits in the RAM bitmap and the LCD elements
the RAM columns and the segment outputs
the RAM rows and the backplane outputs.
A logic 1 in the RAM bitmap indicates the on-state of the corresponding LCD element;
similarly, a logic 0 indicates the off-state.
The display RAM bit map Figure 10 shows the rows 0 to 3 which correspond with the
backplane outputs BP0 to BP3, and the columns 0 to 31 which correspond with the
segment outputs S0 to S31. In multiplexed LCD applications the segment data of the first,
second, third, and fourth row of the display RAM are time-multiplexed with BP0, BP1,
BP2, and BP3 respectively.
When display data is transmitted to the PCF85162, the display bytes received are stored
in the display RAM in accordance with the selected LCD drive mode. The data is stored as
it arrives and does not wait for an acknowledge cycle as with the commands. Depending
on the current multiplex drive mode, data is stored singularly, in pairs, triples or
quadruples. To illustrate the filling order, an example of a 7-segment numeric display
showing all drive modes is given in Figure 11; the RAM filling organization depicted
applies equally to other LCD types.
The display RAM bit map shows the direct relationship between the display RAM addresses and
the segment outputs and between the bits in a RAM word and the backplane outputs.
Fig 10. Display RAM bit map
0
1
2
3
1
2
3
4
27
28
29
30
31
display RAM addresses/segment outputs (S)
columns
display RAM rows/
backplane outputs
(BP)
rows
001aac265
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