參數(shù)資料
型號: PCF85162T/1
廠商: NXP SEMICONDUCTORS
元件分類: 顯示驅動器
英文描述: LIQUID CRYSTAL DISPLAY DRIVER, PDSO48
封裝: 6.10 MM, PLASTIC, MO-153, SOT362-1, TSSOP-48
文件頁數(shù): 14/43頁
文件大?。?/td> 321K
代理商: PCF85162T/1
PCF85162_2
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 02 — 7 May 2010
21 of 43
NXP Semiconductors
PCF85162
Universal LCD driver for low multiplex rates
7.16.5 I2C-bus controller
The PCF85162 acts as an I2C-bus slave receiver. It does not initiate I2C-bus transfers or
transmit data to an I2C-bus master receiver. The only data output from the PCF85162 are
the acknowledge signals of the selected devices. Device selection depends on the
I2C-bus slave address, on the transferred command data and on the hardware
subaddress.
In single device applications, the hardware subaddress inputs A0, A1, and A2 are
normally tied to VSS which defines the hardware subaddress 0. In multiple device
applications A0, A1, and A2 are tied to VSS or VDD using a binary coding scheme, so that
no two devices with a common I2C-bus slave address have the same hardware
subaddress.
7.16.6 Input filters
To enhance noise immunity in electrical adverse environments, RC low-pass filters are
provided on the SDA and SCL lines.
7.16.7 I2C-bus protocol
Two I2C-bus slave addresses (0111 000 and 0111 001) are used to address the
PCF85162. The entire I2C-bus slave address byte is shown in Table 7.
The PCF85162 is a write-only device and will not respond to a read access, therefore bit 0
should always be logic 0. Bit 1 of the slave address byte, that a PCF85162 will respond to,
is defined by the level tied to its SA0 input (VSS for logic 0 and VDD for logic 1).
Fig 15. Acknowledgement of the I2C-bus
mbc602
S
START
condition
9
8
2
1
clock pulse for
acknowledgement
not acknowledge
acknowledge
data output
by transmitter
data output
by receiver
SCL from
master
Table 7.
I2C slave address byte
Slave address
Bit
7
6
5
4
3
2
1
0
MSB
LSB
01
11
00
SA0
R/W
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