參數(shù)資料
型號: PCF85162T/1
廠商: NXP SEMICONDUCTORS
元件分類: 顯示驅(qū)動器
英文描述: LIQUID CRYSTAL DISPLAY DRIVER, PDSO48
封裝: 6.10 MM, PLASTIC, MO-153, SOT362-1, TSSOP-48
文件頁數(shù): 11/43頁
文件大小: 321K
代理商: PCF85162T/1
PCF85162_2
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 02 — 7 May 2010
19 of 43
NXP Semiconductors
PCF85162
Universal LCD driver for low multiplex rates
[1]
The blink frequency is proportional to the clock frequency (fclk). For the range of the clock frequency see
The entire display can blink at a frequency other than the nominal blink frequency. This
can be effectively performed by resetting and setting the display enable bit E at the
required rate using the mode-set command (see Table 10).
7.16 Characteristics of the I2C-bus
The I2C-bus is for bidirectional, two-line communication between different ICs or modules.
The two lines are a Serial DAta line (SDA) and a Serial Clock Line (SCL). Both lines must
be connected to a positive supply via a pull-up resistor when connected to the output
stages of a device. Data transfer may be initiated only when the bus is not busy.
7.16.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as a control signal (see Figure 12).
7.16.2 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy.
A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as the START
condition (S).
A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition (P) (see Figure 13).
Table 6.
Blink frequencies[1]
Blink mode
Blink frequency equation
off
-
1
2
3
f
blink
f
clk
768
----------
=
f
blink
f
clk
1536
-------------
=
f
blink
f
clk
3072
-------------
=
Fig 12. Bit transfer
mba607
data line
stable;
data valid
change
of data
allowed
SDA
SCL
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