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參數(shù)資料
| 型號： | P89C739 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 8-bit Flash microcontrollers |
| 中文描述： | 8位閃存微控制器 |
| 文件頁數(shù)： | 32/64頁 |
| 文件大?。?/td> | 360K |
| 代理商： | P89C739 |
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1998 Apr 07
32
Philips Semiconductors
Product specification
8-bit Flash microcontrollers
P89C738; P89C739
15 RESET
The reset circuitry for the P89C738 is connected to the
reset pin RST. A Schmitt trigger is used at the input for
noise rejection. The output of the Schmitt trigger is
sampled by the reset circuitry every machine cycle.
A reset is accomplished by holding the RST pin HIGH for
at least two machine cycles (24 oscillator periods).
The CPU responds by executing an internal reset. During
reset ALE and PSEN output are at a HIGH level. In order
to perform a correct reset, this level must not be affected
by external elements.
In the P89C738 the internal reset can also be activated by
the Watchdog Timer (T3). If the Watchdog Timer is also
used to reset external devices, the usual capacitor
arrangement should not be connected to RST pin. Instead,
an extra circuit should be used to perform the power-on
reset operation. It should be remembered that a timer T3
overflow, if enabled, will force a reset condition to the
P89C738 by an internal connection, whether the output
RST is tied to LOW or not (see Fig.21).
The internal reset is executed during the second cycle in
which RST is pulled HIGH and is repeated every cycle until
RST goes LOW. It leaves the internal registers as shown
in Chapter 17.
15.1
Power-on reset
Figure 21 shows the on-chip reset configuration.
When V
DD
is turned on, and provided its rise time does not
exceed 10 ms, an automatic reset can be obtained by
connecting the RST pin to V
DD
via a 2.2
μ
F capacitor.
When the power is switched on, the voltage on the RST pin
is equal to V
DD
minus the capacitor voltage, and
decreases from V
DD
as the capacitor charges through the
internal resistor (R
RST
) to ground. The larger the capacitor,
the more slowly V
RST
decreases. V
RST
must remain above
the lower threshold of the Schmitt trigger long enough to
effect a complete reset. The time required is the oscillator
start-up time, plus 2 machine cycles.
Fig.21 On-chip reset configuration.
handbook, full pagewidth
MGK198
SCHMITT
TRIGGER
RESET
CIRCUITRY
RRST
overflow timer T3
RSTOUT
8 k
+
10
μ
F
VDD
on-chip circuit
RST
POC
GND
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