參數(shù)資料
型號： P87CL883T
廠商： NXP Semiconductors N.V.
英文描述： TELX microcontrollers for CT0 handset/basestation applications
中文描述： TELX微控制器CT0手機/基站應用
文件頁數(shù)： 23/32頁
文件大小： 145K
代理商： P87CL883T
23
Philips Semiconductors
Product specification
TELX microcontrollers for CT0
handset/basestation applications
P8xCL883; P8xCL884
Notes
1.
The operating supply current is measured with all output pins disconnected; V
IL
= V
SS
; V
IH
= V
DD
; RST = V
DD
;
XTAL1 driven with square wave; XTAL2 not connected; fetch of NOP instructions; all derivative blocks disabled.
The Idle mode supply current is measured with all output pins and RST disconnected; V
IL
= V
SS
; V
IH
= V
DD
;
XTAL1 driven with square wave; XTAL2 not connected; all derivative blocks disabled.
The Power-down current is measured with all output pins and RST disconnected; V
IL
= V
SS
; V
IH
= V
DD
;
XTAL1 and XTAL2 not connected;.
The typical currents are only for the specific block. To calculate the typical power consumption of the microcontroller,
the current consumption of the CPU must be added. Example: the typical current consumption of the microcontroller
in operating mode with CPU, Watchdog and UART active can be calculated as (1.8 + 0.11 + 0.09) mA = 2.0 mA.
Verified on sampling basis.
The input threshold voltage of P1.6/SCL and P1.7/SDA meet the I
2
C-bus specification. Therefore, an input voltage
below 0.3V
DD
will be recognized as a logic 0 and an input voltage above 0.7V
DD
will be recognized as a logic 1.
For pin PORENABLE the V
IL(max)
= 0.1V
DD
.
Not valid for pins SDA, SCL, RST, MIN and PORENABLE.
The maximum allowed load capacitance C
L
is in this case limited to around 200 pF.
10. The LVD is tested according to the specification in the data sheet “TELX family; Chapter: Low Voltage Detection”
11. Values are specified for DTMF frequencies only (CEPT CS203).
12. Related to the Low Group Frequency (LGF) component (CEPT CS203).
13. After final testing the value of each EEPROM bit is typically logic 1.
14. Can also be done by two 100
μ
s pulses.
15. C
1i
and C
2i
are the total internal capacitances (including gate capacitance, leadframe capacitance).
2.
3.
4.
5.
6.
7.
8.
9.
In-System Programming for the OTP
t
prog
t
ver
t
Vpp(setup)
t
Vpp(max)
program cycle time
verify cycle time
program voltage setup time
maximum program voltage time
90
1
10
100
110
60
μ
s
μ
s
μ
s
s
cumulative for the
product lifetime
In-System Programming
I
Vpp
program voltage current
40
mA
ACO (Amplitude Controlled Oscillator)
V
XTAL1
external clock signal amplitude
peak-to-peak
input impedance on XTAL1
input capacitance on XTAL1 and XTAL2
500
V
DD
mV
Z
i(XTAL1)
C
1i
; C
2i
300
1000
10
k
pF
notes 5 and 15
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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